29 #define QQQdialect MPLABX 43 #undef QQQMULTIPROCESSEXH 46 #define qqqMaxBranchDepth 20 47 #define QQQstructbitmap 59 #undef QQQTEMPLATEONLY 61 #define QQQUPLOADATEND 63 #undef QQQASHLINGVITRA 65 #define qqqbitmapint unsigned int 67 #undef QQQTIC2XSERIALIO 69 #undef QQQCOMPRESSED_EXH 76 #define adc_63zzopen zzopen 78 #define adc_63zqqzqz1 zqqzqz1 81 #define FILEPOINT FILE * f, 82 #if !defined(QQQTEMPLATEONLY) && !defined(FILE) && !defined(QQQNOSTDIO) 98 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port.h" 99 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port_common.h" 102 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port.c" 103 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port_common.c" 111 #if defined(QQQstructbitmap) && defined(QQQSINGLEFILE) 112 #ifndef LDRA_VOID_FUNC 113 #define LDRA_VOID_FUNC 116 #if defined(QQQMAINFL) 139 #ifdef QQQ_KEEPCOMMENTS 147 #if !defined(QQQSUPPRESS_UNDEF) 153 #undef QQQHITMAP_STORAGE 155 #define qqnull_params void 156 #define QQQ_PROTOTYPE_DEF 158 #undef QQ_ANSI_PROTOTYPE 160 #define QQ_ANSI_PROTOTYPE 1 163 #define QQ_ANSI_PROTOTYPE 1 169 #define ELEMENT(N) qqqbitmapint element##N; 171 #include "adc_63zbelem.def" 175 #define ELEMENT(N) 0, 177 #include "adc_63zbelem.def" 259 uint16_t wl_sps_i_cf ;
339 #ifndef _SYS_DEFINITIONS_H 340 #define _SYS_DEFINITIONS_H 349 #include "system/common/sys_common.h" 350 #include "system/common/sys_module.h" 434 #ifndef _SYSTEM_CONFIG_H 435 #define _SYSTEM_CONFIG_H 454 #define SYS_VERSION_STR "2.06" 455 #define SYS_VERSION 20600 459 #define SYS_CLK_FREQ 200000000ul 460 #define SYS_CLK_BUS_PERIPHERAL_1 100000000ul 461 #define SYS_CLK_BUS_PERIPHERAL_2 100000000ul 462 #define SYS_CLK_BUS_PERIPHERAL_3 100000000ul 463 #define SYS_CLK_BUS_PERIPHERAL_4 100000000ul 464 #define SYS_CLK_BUS_PERIPHERAL_5 100000000ul 465 #define SYS_CLK_BUS_PERIPHERAL_7 200000000ul 466 #define SYS_CLK_BUS_PERIPHERAL_8 100000000ul 467 #define SYS_CLK_CONFIG_PRIMARY_XTAL 0ul 468 #define SYS_CLK_CONFIG_SECONDARY_XTAL 32768ul 470 #define SYS_PORT_A_ANSEL 0x3F00 471 #define SYS_PORT_A_TRIS 0xFFED 472 #define SYS_PORT_A_LAT 0x0010 473 #define SYS_PORT_A_ODC 0x0000 474 #define SYS_PORT_A_CNPU 0x0020 475 #define SYS_PORT_A_CNPD 0x0000 476 #define SYS_PORT_A_CNEN 0x0021 477 #define SYS_PORT_B_ANSEL 0x10C8 478 #define SYS_PORT_B_TRIS 0x91FF 479 #define SYS_PORT_B_LAT 0x0000 480 #define SYS_PORT_B_ODC 0x0000 481 #define SYS_PORT_B_CNPU 0x0000 482 #define SYS_PORT_B_CNPD 0x0000 483 #define SYS_PORT_B_CNEN 0x0000 484 #define SYS_PORT_C_ANSEL 0xCFE1 485 #define SYS_PORT_C_TRIS 0xFFFF 486 #define SYS_PORT_C_LAT 0x0000 487 #define SYS_PORT_C_ODC 0x0000 488 #define SYS_PORT_C_CNPU 0x0000 489 #define SYS_PORT_C_CNPD 0x0000 490 #define SYS_PORT_C_CNEN 0x0000 491 #define SYS_PORT_D_ANSEL 0xC100 492 #define SYS_PORT_D_TRIS 0xFFFF 493 #define SYS_PORT_D_LAT 0x0000 494 #define SYS_PORT_D_ODC 0x0000 495 #define SYS_PORT_D_CNPU 0x0000 496 #define SYS_PORT_D_CNPD 0x0000 497 #define SYS_PORT_D_CNEN 0x0000 498 #define SYS_PORT_E_ANSEL 0xFC00 499 #define SYS_PORT_E_TRIS 0xFDFF 500 #define SYS_PORT_E_LAT 0x0000 501 #define SYS_PORT_E_ODC 0x0000 502 #define SYS_PORT_E_CNPU 0x0000 503 #define SYS_PORT_E_CNPD 0x0000 504 #define SYS_PORT_E_CNEN 0x0000 505 #define SYS_PORT_F_ANSEL 0xCEC0 506 #define SYS_PORT_F_TRIS 0xEFFF 507 #define SYS_PORT_F_LAT 0x0000 508 #define SYS_PORT_F_ODC 0x0000 509 #define SYS_PORT_F_CNPU 0x0000 510 #define SYS_PORT_F_CNPD 0x0000 511 #define SYS_PORT_F_CNEN 0x0000 512 #define SYS_PORT_G_ANSEL 0x8CBC 513 #define SYS_PORT_G_TRIS 0xDFFF 514 #define SYS_PORT_G_LAT 0x0000 515 #define SYS_PORT_G_ODC 0x0000 516 #define SYS_PORT_G_CNPU 0x0000 517 #define SYS_PORT_G_CNPD 0x0000 518 #define SYS_PORT_G_CNEN 0x0000 519 #define SYS_PORT_H_ANSEL 0x0070 520 #define SYS_PORT_H_TRIS 0xB3FB 521 #define SYS_PORT_H_LAT 0x0000 522 #define SYS_PORT_H_ODC 0x0000 523 #define SYS_PORT_H_CNPU 0x0000 524 #define SYS_PORT_H_CNPD 0x0000 525 #define SYS_PORT_H_CNEN 0x0000 526 #define SYS_PORT_J_ANSEL 0x0000 527 #define SYS_PORT_J_TRIS 0x8B7F 528 #define SYS_PORT_J_LAT 0x0080 529 #define SYS_PORT_J_ODC 0x0000 530 #define SYS_PORT_J_CNPU 0x0000 531 #define SYS_PORT_J_CNPD 0x0000 532 #define SYS_PORT_J_CNEN 0x0800 533 #define SYS_PORT_K_ANSEL 0xFF00 534 #define SYS_PORT_K_TRIS 0xFFFF 535 #define SYS_PORT_K_LAT 0x0000 536 #define SYS_PORT_K_ODC 0x0000 537 #define SYS_PORT_K_CNPU 0x0000 538 #define SYS_PORT_K_CNPD 0x0000 539 #define SYS_PORT_K_CNEN 0x0000 543 #define SYS_TMR_POWER_STATE SYS_MODULE_POWER_RUN_FULL 544 #define SYS_TMR_DRIVER_INDEX DRV_TMR_INDEX_0 545 #define SYS_TMR_MAX_CLIENT_OBJECTS 5 546 #define SYS_TMR_FREQUENCY 1000 547 #define SYS_TMR_FREQUENCY_TOLERANCE 10 548 #define SYS_TMR_UNIT_RESOLUTION 10000 549 #define SYS_TMR_CLIENT_TOLERANCE 10 550 #define SYS_TMR_INTERRUPT_NOTIFICATION false 556 #define DRV_IC_DRIVER_MODE_STATIC 559 #define DRV_SPI_NUMBER_OF_MODULES 6 562 #define DRV_SPI_POLLED 1 563 #define DRV_SPI_ISR 0 564 #define DRV_SPI_MASTER 1 565 #define DRV_SPI_SLAVE 0 567 #define DRV_SPI_EBM 1 568 #define DRV_SPI_8BIT 1 569 #define DRV_SPI_16BIT 1 570 #define DRV_SPI_32BIT 0 571 #define DRV_SPI_DMA 0 573 #define DRV_SPI_INSTANCES_NUMBER 3 574 #define DRV_SPI_CLIENTS_NUMBER 3 575 #define DRV_SPI_ELEMENTS_PER_QUEUE 10 577 #define DRV_SPI_SPI_ID_IDX0 SPI_ID_1 578 #define DRV_SPI_TASK_MODE_IDX0 DRV_SPI_TASK_MODE_POLLED 579 #define DRV_SPI_SPI_MODE_IDX0 DRV_SPI_MODE_MASTER 580 #define DRV_SPI_ALLOW_IDLE_RUN_IDX0 false 581 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX0 DRV_SPI_PROTOCOL_TYPE_FRAMED 582 #define DRV_SPI_FRAME_SYNC_PULSE_IDX0 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 583 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX0 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 584 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX0 SPI_FRAME_PULSE_DIRECTION_OUTPUT 585 #define DRV_SPI_FRAME_PULSE_EDGE_IDX0 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 586 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX0 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 587 #define DRV_SPI_COMM_WIDTH_IDX0 SPI_COMMUNICATION_WIDTH_16BITS 588 #define DRV_SPI_CLOCK_SOURCE_IDX0 SPI_BAUD_RATE_PBCLK_CLOCK 589 #define DRV_SPI_SPI_CLOCK_IDX0 CLK_BUS_PERIPHERAL_2 590 #define DRV_SPI_BAUD_RATE_IDX0 1000000 591 #define DRV_SPI_BUFFER_TYPE_IDX0 DRV_SPI_BUFFER_TYPE_ENHANCED 592 #define DRV_SPI_CLOCK_MODE_IDX0 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 593 #define DRV_SPI_INPUT_PHASE_IDX0 SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE 594 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX0 0xFFFF 595 #define DRV_SPI_QUEUE_SIZE_IDX0 10 596 #define DRV_SPI_RESERVED_JOB_IDX0 1 598 #define DRV_SPI_SPI_ID_IDX1 SPI_ID_2 599 #define DRV_SPI_TASK_MODE_IDX1 DRV_SPI_TASK_MODE_POLLED 600 #define DRV_SPI_SPI_MODE_IDX1 DRV_SPI_MODE_MASTER 601 #define DRV_SPI_ALLOW_IDLE_RUN_IDX1 false 602 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX1 DRV_SPI_PROTOCOL_TYPE_FRAMED 603 #define DRV_SPI_FRAME_SYNC_PULSE_IDX1 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 604 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX1 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 605 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX1 SPI_FRAME_PULSE_DIRECTION_OUTPUT 606 #define DRV_SPI_FRAME_PULSE_EDGE_IDX1 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 607 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX1 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 608 #define DRV_SPI_COMM_WIDTH_IDX1 SPI_COMMUNICATION_WIDTH_8BITS 609 #define DRV_SPI_CLOCK_SOURCE_IDX1 SPI_BAUD_RATE_PBCLK_CLOCK 610 #define DRV_SPI_SPI_CLOCK_IDX1 CLK_BUS_PERIPHERAL_2 611 #define DRV_SPI_BAUD_RATE_IDX1 1000000 612 #define DRV_SPI_BUFFER_TYPE_IDX1 DRV_SPI_BUFFER_TYPE_ENHANCED 613 #define DRV_SPI_CLOCK_MODE_IDX1 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 614 #define DRV_SPI_INPUT_PHASE_IDX1 SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE 615 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX1 0xFF 616 #define DRV_SPI_QUEUE_SIZE_IDX1 10 617 #define DRV_SPI_RESERVED_JOB_IDX1 1 619 #define DRV_SPI_SPI_ID_IDX2 SPI_ID_4 620 #define DRV_SPI_TASK_MODE_IDX2 DRV_SPI_TASK_MODE_POLLED 621 #define DRV_SPI_SPI_MODE_IDX2 DRV_SPI_MODE_MASTER 622 #define DRV_SPI_ALLOW_IDLE_RUN_IDX2 false 623 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX2 DRV_SPI_PROTOCOL_TYPE_FRAMED 624 #define DRV_SPI_FRAME_SYNC_PULSE_IDX2 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 625 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX2 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 626 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX2 SPI_FRAME_PULSE_DIRECTION_OUTPUT 627 #define DRV_SPI_FRAME_PULSE_EDGE_IDX2 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 628 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX2 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 629 #define DRV_SPI_COMM_WIDTH_IDX2 SPI_COMMUNICATION_WIDTH_16BITS 630 #define DRV_SPI_CLOCK_SOURCE_IDX2 SPI_BAUD_RATE_PBCLK_CLOCK 631 #define DRV_SPI_SPI_CLOCK_IDX2 CLK_BUS_PERIPHERAL_2 632 #define DRV_SPI_BAUD_RATE_IDX2 500000 633 #define DRV_SPI_BUFFER_TYPE_IDX2 DRV_SPI_BUFFER_TYPE_ENHANCED 634 #define DRV_SPI_CLOCK_MODE_IDX2 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 635 #define DRV_SPI_INPUT_PHASE_IDX2 SPI_INPUT_SAMPLING_PHASE_AT_END 636 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX2 0x0000 637 #define DRV_SPI_QUEUE_SIZE_IDX2 10 638 #define DRV_SPI_RESERVED_JOB_IDX2 1 640 #define DRV_TMR_INTERRUPT_MODE true 642 #define DRV_TMR_PERIPHERAL_ID_IDX0 TMR_ID_2 643 #define DRV_TMR_INTERRUPT_SOURCE_IDX0 INT_SOURCE_TIMER_2 644 #define DRV_TMR_INTERRUPT_VECTOR_IDX0 INT_VECTOR_T2 645 #define DRV_TMR_ISR_VECTOR_IDX0 _TIMER_2_VECTOR 646 #define DRV_TMR_INTERRUPT_PRIORITY_IDX0 INT_PRIORITY_LEVEL4 647 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX0 INT_SUBPRIORITY_LEVEL0 648 #define DRV_TMR_CLOCK_SOURCE_IDX0 DRV_TMR_CLKSOURCE_INTERNAL 649 #define DRV_TMR_PRESCALE_IDX0 TMR_PRESCALE_VALUE_8 650 #define DRV_TMR_OPERATION_MODE_IDX0 DRV_TMR_OPERATION_MODE_16_BIT 651 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX0 false 652 #define DRV_TMR_POWER_STATE_IDX0 653 #define DRV_TMR_PERIPHERAL_ID_IDX1 TMR_ID_7 654 #define DRV_TMR_INTERRUPT_SOURCE_IDX1 INT_SOURCE_TIMER_7 655 #define DRV_TMR_INTERRUPT_VECTOR_IDX1 INT_VECTOR_T7 656 #define DRV_TMR_ISR_VECTOR_IDX1 _TIMER_7_VECTOR 657 #define DRV_TMR_INTERRUPT_PRIORITY_IDX1 INT_PRIORITY_LEVEL3 658 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX1 INT_SUBPRIORITY_LEVEL0 659 #define DRV_TMR_CLOCK_SOURCE_IDX1 DRV_TMR_CLKSOURCE_INTERNAL 660 #define DRV_TMR_PRESCALE_IDX1 TMR_PRESCALE_VALUE_16 661 #define DRV_TMR_OPERATION_MODE_IDX1 DRV_TMR_OPERATION_MODE_16_BIT 662 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX1 false 663 #define DRV_TMR_POWER_STATE_IDX1 665 #define DRV_TMR_PERIPHERAL_ID_IDX2 TMR_ID_6 666 #define DRV_TMR_INTERRUPT_SOURCE_IDX2 INT_SOURCE_TIMER_6 667 #define DRV_TMR_INTERRUPT_VECTOR_IDX2 INT_VECTOR_T6 668 #define DRV_TMR_ISR_VECTOR_IDX2 _TIMER_6_VECTOR 669 #define DRV_TMR_INTERRUPT_PRIORITY_IDX2 INT_PRIORITY_LEVEL1 670 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX2 INT_SUBPRIORITY_LEVEL0 671 #define DRV_TMR_CLOCK_SOURCE_IDX2 DRV_TMR_CLKSOURCE_INTERNAL 672 #define DRV_TMR_PRESCALE_IDX2 TMR_PRESCALE_VALUE_16 673 #define DRV_TMR_OPERATION_MODE_IDX2 DRV_TMR_OPERATION_MODE_16_BIT 674 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX2 false 675 #define DRV_TMR_POWER_STATE_IDX2 677 #define DRV_TMR_PERIPHERAL_ID_IDX3 TMR_ID_1 678 #define DRV_TMR_INTERRUPT_SOURCE_IDX3 INT_SOURCE_TIMER_1 679 #define DRV_TMR_INTERRUPT_VECTOR_IDX3 INT_VECTOR_T1 680 #define DRV_TMR_ISR_VECTOR_IDX3 _TIMER_1_VECTOR 681 #define DRV_TMR_INTERRUPT_PRIORITY_IDX3 INT_PRIORITY_LEVEL2 682 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX3 INT_SUBPRIORITY_LEVEL0 683 #define DRV_TMR_CLOCK_SOURCE_IDX3 DRV_TMR_CLKSOURCE_INTERNAL 684 #define DRV_TMR_PRESCALE_IDX3 TMR_PRESCALE_VALUE_256 685 #define DRV_TMR_OPERATION_MODE_IDX3 DRV_TMR_OPERATION_MODE_16_BIT 686 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX3 false 687 #define DRV_TMR_POWER_STATE_IDX3 689 #define DRV_TMR_PERIPHERAL_ID_IDX4 TMR_ID_3 690 #define DRV_TMR_INTERRUPT_SOURCE_IDX4 INT_SOURCE_TIMER_3 691 #define DRV_TMR_INTERRUPT_VECTOR_IDX4 INT_VECTOR_T3 692 #define DRV_TMR_ISR_VECTOR_IDX4 _TIMER_3_VECTOR 693 #define DRV_TMR_INTERRUPT_PRIORITY_IDX4 INT_PRIORITY_LEVEL1 694 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX4 INT_SUBPRIORITY_LEVEL0 695 #define DRV_TMR_CLOCK_SOURCE_IDX4 DRV_TMR_CLKSOURCE_INTERNAL 696 #define DRV_TMR_PRESCALE_IDX4 TMR_PRESCALE_VALUE_16 697 #define DRV_TMR_OPERATION_MODE_IDX4 DRV_TMR_OPERATION_MODE_16_BIT 698 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX4 false 699 #define DRV_TMR_POWER_STATE_IDX4 703 #define DRV_USART_INSTANCES_NUMBER 1 704 #define DRV_USART_CLIENTS_NUMBER 1 705 #define DRV_USART_INTERRUPT_MODE false 706 #define DRV_USART_BYTE_MODEL_SUPPORT true 707 #define DRV_USART_READ_WRITE_MODEL_SUPPORT false 708 #define DRV_USART_BUFFER_QUEUE_SUPPORT false 716 #define DRV_USBHS_DEVICE_SUPPORT true 718 #define DRV_USBHS_HOST_SUPPORT false 720 #define DRV_USBHS_INSTANCES_NUMBER 1 722 #define DRV_USBHS_INTERRUPT_MODE true 724 #define DRV_USBHS_ENDPOINTS_NUMBER 2 727 #define USB_DEVICE_DRIVER_INITIALIZE_EXPLICIT 729 #define USB_DEVICE_INSTANCES_NUMBER 1 731 #define USB_DEVICE_EP0_BUFFER_SIZE 64 733 #define USB_DEVICE_ENDPOINT_QUEUE_DEPTH_COMBINED 2 741 #define LED1Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 742 #define LED1On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 743 #define LED1Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 744 #define LED1StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 745 #define LED1StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 , Value ) 747 #define LED2Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 748 #define LED2On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 749 #define LED2Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 750 #define LED2StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 751 #define LED2StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 , Value ) 753 #define DMP_FIRE_LEDToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 754 #define DMP_FIRE_LEDOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 755 #define DMP_FIRE_LEDOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 756 #define DMP_FIRE_LEDStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 757 #define DMP_FIRE_LEDStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 , Value ) 759 #define HVPS_ENBToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 760 #define HVPS_ENBOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 761 #define HVPS_ENBOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 762 #define HVPS_ENBStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 763 #define HVPS_ENBStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 , Value ) 765 #define RLY_HVPS_OUTToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 766 #define RLY_HVPS_OUTOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 767 #define RLY_HVPS_OUTOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 768 #define RLY_HVPS_OUTStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 769 #define RLY_HVPS_OUTStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 , Value ) 771 #define RLY_WL_SPS_POLToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 772 #define RLY_WL_SPS_POLOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 773 #define RLY_WL_SPS_POLOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 774 #define RLY_WL_SPS_POLStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 775 #define RLY_WL_SPS_POLStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 , Value ) 777 #define RLY_LOGToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 778 #define RLY_LOGOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 779 #define RLY_LOGOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 780 #define RLY_LOGStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 781 #define RLY_LOGStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 , Value ) 783 #define RLY_DMP_FIREToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 784 #define RLY_DMP_FIREOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 785 #define RLY_DMP_FIREOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 786 #define RLY_DMP_FIREStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 787 #define RLY_DMP_FIREStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 , Value ) 789 #define RLY_AUXToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 790 #define RLY_AUXOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 791 #define RLY_AUXOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 792 #define RLY_AUXStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 793 #define RLY_AUXStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 , Value ) 795 #define RLY_CCLToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 796 #define RLY_CCLOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 797 #define RLY_CCLOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 798 #define RLY_CCLStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 799 #define RLY_CCLStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 , Value ) 801 #define RLY_WL_MONToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 802 #define RLY_WL_MONOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 803 #define RLY_WL_MONOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 804 #define RLY_WL_MONStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 805 #define RLY_WL_MONStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 , Value ) 807 #define RLY_ARMCFToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 808 #define RLY_ARMCFOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 809 #define RLY_ARMCFOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 810 #define RLY_ARMCFStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 811 #define RLY_ARMCFStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 , Value ) 813 #define RLY_ARMToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 814 #define RLY_ARMOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 815 #define RLY_ARMOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 816 #define RLY_ARMStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 817 #define RLY_ARMStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 , Value ) 819 #define TPAN1Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 820 #define TPAN1On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 821 #define TPAN1Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 822 #define TPAN1StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 823 #define TPAN1StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 , Value ) 825 #define TPAN2Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 826 #define TPAN2On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 827 #define TPAN2Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 828 #define TPAN2StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 829 #define TPAN2StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 , Value ) 831 #define FSK_DAC_CSToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 832 #define FSK_DAC_CSOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 833 #define FSK_DAC_CSOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 834 #define FSK_DAC_CSStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 835 #define FSK_DAC_CSStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 , Value ) 837 #define RLY_COMMToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 838 #define RLY_COMMOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 839 #define RLY_COMMOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 840 #define RLY_COMMStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 841 #define RLY_COMMStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 , Value ) 843 #define FSK_DAC_CLRToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 844 #define FSK_DAC_CLROn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 845 #define FSK_DAC_CLROff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 846 #define FSK_DAC_CLRStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 847 #define FSK_DAC_CLRStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 , Value ) 849 #define WL_CPS_SWToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 850 #define WL_CPS_SWOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 851 #define WL_CPS_SWOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 852 #define WL_CPS_SWStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 853 #define WL_CPS_SWStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 , Value ) 855 #define HVPS_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_5 ) 857 #define MAN_SIGStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_0 ) 859 #define DMP_FIRE_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_8 ) 861 #define NEG_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_4 ) 863 #define POS_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_15 ) 865 #define DRUM1_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_2 ) 867 #define SAFE_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_1 ) 869 #define DRUM2_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_0 ) 871 #define LOG_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_3 ) 873 #define AUX_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_8 ) 875 #define ARMCF_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_K , PORTS_BIT_POS_1 ) 877 #define ARM_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_K , PORTS_BIT_POS_2 ) 879 #define ARMCF_AUTO_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_13 ) 881 #define FIRE_SW_OFFStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_8 ) 883 #define FIRE_SW_ONStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_8 ) 885 #define WL_SPS_POS_DETStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_12 ) 887 #define WL_SPS_NEG_DETStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_13 ) 888 #define MAN_CN_PORT_CHANNEL PORT_CHANNEL_A 889 #define MAN_CN_PORT_BIT PORTS_BIT_POS_0 890 #define MAN_CN_PORT_INTERRUPT INT_SOURCE_CHANGE_NOTICE_A 891 #define HVPS_CN_PORT_CHANNEL PORT_CHANNEL_J 892 #define HVPS_CN_PORT_BIT PORTS_BIT_POS_11 893 #define HVPS_CN_PORT_INTERRUPT INT_SOURCE_CHANGE_NOTICE_J 942 #ifndef _DRV_COMMON_H 943 #define _DRV_COMMON_H 1045 #define DRV_IO_ISBLOCKING( intent ) ( intent & DRV_IO_INTENT_BLOCKING ) 1055 #define DRV_IO_ISNONBLOCKING( intent ) ( intent & DRV_IO_INTENT_NONBLOCKING ) 1065 #define DRV_IO_ISEXCLUSIVE( intent ) ( intent & DRV_IO_INTENT_EXCLUSIVE ) 1121 #define DRV_HANDLE_INVALID ( ( ( DRV_HANDLE ) - 1 ) ) 1132 #define DRV_CONFIG_NOT_SUPPORTED ( ( ( unsigned short ) - 1 ) ) 1147 #define _PLIB_UNSUPPORTED 1155 #include "system/common/sys_module.h" 1167 #define DRV_IC_INDEX_0 0 1168 #define DRV_IC_INDEX_1 1 1169 #define DRV_IC_INDEX_2 2 1170 #define DRV_IC_INDEX_3 3 1171 #define DRV_IC_INDEX_4 4 1172 #define DRV_IC_INDEX_5 5 1173 #define DRV_IC_INDEX_6 6 1174 #define DRV_IC_INDEX_7 7 1175 #define DRV_IC_INDEX_8 8 1176 #define DRV_IC_INDEX_9 9 1177 #define DRV_IC_INDEX_10 10 1178 #define DRV_IC_INDEX_11 11 1179 #define DRV_IC_INDEX_12 12 1180 #define DRV_IC_INDEX_13 13 1181 #define DRV_IC_INDEX_14 14 1182 #define DRV_IC_INDEX_15 15 1214 const SYS_MODULE_INDEX index ,
1215 const SYS_MODULE_INIT *
const init ) ;
1237 const SYS_MODULE_INDEX drvIndex ,
1282 const SYS_MODULE_INDEX drvIndex ,
1415 #ifndef _DRV_IC_STATIC_H 1416 #define _DRV_IC_STATIC_H 1417 #define DRV_IC_Open( drvIndex , intent ) ( drvIndex ) 1418 #define DRV_IC_Close( handle ) 1457 #include "system/devcon/sys_devcon.h" 1458 #include "system/clk/sys_clk.h" 1459 #include "system/int/sys_int.h" 1460 #include "system/tmr/sys_tmr.h" 1502 #ifndef _DRV_ADC_STATIC_H 1503 #define _DRV_ADC_STATIC_H 1504 #include <stdbool.h> 1505 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 1506 #include "peripheral/adchs/plib_adchs.h" 1507 #include "peripheral/int/plib_int.h" 1547 uint8_t bufIndex ) ;
1551 uint8_t bufIndex ) ;
1601 #ifndef _DRV_TMR_STATIC_H 1602 #define _DRV_TMR_STATIC_H 1651 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 1652 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 1653 #include "peripheral/tmr/plib_tmr.h" 1689 #ifndef _TMR_DEFINITIONS_PIC32M_H 1690 #define _TMR_DEFINITIONS_PIC32M_H 1748 #include "system/int/sys_int.h" 1749 #include "system/clk/sys_clk.h" 1768 #define DRV_TMR_INDEX_0 0 1769 #define DRV_TMR_INDEX_1 1 1770 #define DRV_TMR_INDEX_2 2 1771 #define DRV_TMR_INDEX_3 3 1772 #define DRV_TMR_INDEX_4 4 1773 #define DRV_TMR_INDEX_5 5 1774 #define DRV_TMR_INDEX_6 6 1775 #define DRV_TMR_INDEX_7 7 1776 #define DRV_TMR_INDEX_8 8 1777 #define DRV_TMR_INDEX_9 9 1778 #define DRV_TMR_INDEX_10 10 1779 #define DRV_TMR_INDEX_11 11 1790 #define DRV_TMR_INDEX_COUNT TMR_NUMBER_OF_MODULES 1929 uint32_t alarmCount ) ;
1991 const SYS_MODULE_INDEX drvIndex ,
1992 const SYS_MODULE_INIT *
const init ) ;
2032 SYS_MODULE_OBJ
object ) ;
2079 SYS_MODULE_OBJ
object ) ;
2113 SYS_MODULE_OBJ
object ) ;
2167 const SYS_MODULE_INDEX index ,
2268 uint32_t counterPeriod ) ;
2758 TMR_PRESCALE preScale ) ;
2998 #ifndef _DRV_TMR_DEPRECATED_H 2999 #define _DRV_TMR_DEPRECATED_H 3040 #define DRV_TMR_Tasks_ISR( object ) DRV_TMR_Tasks ( object ) 3104 #define DRV_TMR_CounterValue16BitSet( handle , counterPeriod ) DRV_TMR_CounterValueSet ( handle , counterPeriod ) 3169 #define DRV_TMR_CounterValue32BitSet( handle , counterPeriod ) DRV_TMR_CounterValueSet ( handle , counterPeriod ) 3228 #define DRV_TMR_CounterValue16BitGet( handle ) DRV_TMR_CounterValueGet ( handle ) 3289 #define DRV_TMR_CounterValue32BitGet( handle ) DRV_TMR_CounterValueGet ( handle ) 3348 #define DRV_TMR_Alarm16BitRegister( handle , period , isPeriodic , context , callBack ) DRV_TMR_AlarmRegister ( handle , period , isPeriodic , context , callBack ) 3409 #define DRV_TMR_Alarm32BitRegister( handle , period , isPeriodic , context , callBack ) DRV_TMR_AlarmRegister ( handle , period , isPeriodic , context , callBack ) 3439 #define DRV_TMR_AlarmPeriod16BitSet( handle , value ) DRV_TMR_AlarmPeriodSet ( handle , value ) 3471 #define DRV_TMR_AlarmPeriod32BitSet( handle , period ) DRV_TMR_AlarmPeriodSet ( handle , period ) 3502 #define DRV_TMR_AlarmPeriod16BitGet( handle ) DRV_TMR_AlarmPeriodGet ( handle ) 3534 #define DRV_TMR_AlarmPeriod32BitGet( handle ) DRV_TMR_AlarmPeriodGet ( handle ) 3596 #define DRV_TMR_Alarm16BitDeregister( handle ) DRV_TMR_AlarmDeregister ( handle ) 3661 #define DRV_TMR_Alarm32BitDeregister( handle ) DRV_TMR_AlarmDeregister ( handle ) 3678 #include "peripheral/tmr/plib_tmr.h" 3679 #include "peripheral/int/plib_int.h" 3681 #define DRV_TIMER_DIVIDER_MAX_32BIT 0xffffffff 3683 #define DRV_TIMER_DIVIDER_MIN_32BIT 0x2 3685 #define DRV_TIMER_DIVIDER_MAX_16BIT 0x10000 3687 #define DRV_TIMER_DIVIDER_MIN_16BIT 0x2 3706 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 0)));
3712 static inline SYS_STATUS
3715 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 2)));
3726 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 4)));
3737 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 6)));
3747 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 8)));
3756 TMR_PRESCALE prescale ) ;
3787 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 10)));
3816 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 12)));
3822 static inline SYS_STATUS
3825 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 14)));
3836 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 16)));
3847 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 18)));
3857 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 20)));
3866 TMR_PRESCALE prescale ) ;
3897 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 22)));
3926 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 24)));
3932 static inline SYS_STATUS
3935 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 26)));
3946 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 28)));
3957 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 30)));
3967 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 0)));
3976 TMR_PRESCALE prescale ) ;
4007 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 2)));
4036 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 4)));
4042 static inline SYS_STATUS
4045 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 6)));
4056 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 8)));
4067 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 10)));
4077 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 12)));
4086 TMR_PRESCALE prescale ) ;
4117 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 14)));
4146 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 16)));
4152 static inline SYS_STATUS
4155 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 18)));
4166 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 20)));
4177 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 22)));
4187 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 24)));
4196 TMR_PRESCALE prescale ) ;
4227 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 26)));
4246 #include "peripheral/int/plib_int.h" 4288 #ifndef _DRV_PMP_STATIC_H 4289 #define _DRV_PMP_STATIC_H 4290 #include "peripheral/pmp/plib_pmp.h" 4305 PMP_DATA_WAIT_STATES dataWait ,
4306 PMP_STROBE_WAIT_STATES strobeWait ,
4307 PMP_DATA_HOLD_STATES dataHold ) ;
4362 #ifndef _DRV_USART_STATIC_H 4363 #define _DRV_USART_STATIC_H 4402 #ifndef _DRV_USART_STATIC_LOCAL_H 4403 #define _DRV_USART_STATIC_LOCAL_H 4410 #include <stdbool.h> 4447 #ifndef _DRV_USART_H 4448 #define _DRV_USART_H 4488 #ifndef _DRV_USART_DEFINITIONS_H 4489 #define _DRV_USART_DEFINITIONS_H 4495 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 4496 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 4533 #ifndef _PLIB_USART_H 4534 #define _PLIB_USART_H 4577 #ifndef _USART_PROCESSOR_H 4578 #define _USART_PROCESSOR_H 4587 #include <stdbool.h> 4588 #error "No Processor Family specified" 4632 USART_MODULE_ID index ) ;
4662 USART_MODULE_ID index ) ;
4694 USART_MODULE_ID index ) ;
4728 USART_MODULE_ID index ,
4729 USART_BRG_CLOCK_SOURCE brgClockSource ) ;
4758 USART_BRG_CLOCK_SOURCE
4760 USART_MODULE_ID index ) ;
4814 USART_MODULE_ID index ) ;
4844 USART_MODULE_ID index ) ;
4873 USART_MODULE_ID index ) ;
4905 USART_MODULE_ID index ) ;
4936 USART_MODULE_ID index ) ;
4978 USART_MODULE_ID index ) ;
5011 USART_MODULE_ID index ) ;
5043 USART_MODULE_ID index ) ;
5084 USART_MODULE_ID index ,
5085 uint32_t clockFrequency ,
5086 uint32_t baudRate ) ;
5127 USART_MODULE_ID index ,
5128 uint32_t clockFrequency ,
5129 uint32_t baudRate ) ;
5162 USART_MODULE_ID index ,
5163 int32_t clockFrequency ) ;
5198 USART_MODULE_ID index ,
5233 USART_MODULE_ID index ) ;
5268 USART_MODULE_ID index ,
5303 USART_MODULE_ID index ) ;
5335 USART_MODULE_ID index ) ;
5369 USART_MODULE_ID index ) ;
5402 USART_MODULE_ID index ) ;
5435 USART_MODULE_ID index ) ;
5469 USART_MODULE_ID index ,
5514 USART_MODULE_ID index ) ;
5548 USART_MODULE_ID index ) ;
5584 USART_MODULE_ID index ) ;
5621 USART_MODULE_ID index ,
5661 USART_MODULE_ID index ) ;
5699 USART_MODULE_ID index ) ;
5734 USART_MODULE_ID index ) ;
5768 USART_MODULE_ID index ) ;
5802 USART_MODULE_ID index ) ;
5835 USART_MODULE_ID index ) ;
5867 USART_MODULE_ID index ) ;
5899 USART_MODULE_ID index ) ;
5932 USART_MODULE_ID index ) ;
5966 USART_MODULE_ID index ) ;
5995 USART_MODULE_ID index ) ;
6024 USART_MODULE_ID index ) ;
6056 USART_MODULE_ID index ) ;
6088 USART_MODULE_ID index ) ;
6118 USART_MODULE_ID index ) ;
6148 USART_MODULE_ID index ) ;
6177 USART_MODULE_ID index ) ;
6206 USART_MODULE_ID index ) ;
6240 USART_MODULE_ID index ,
6241 USART_TRANSMIT_INTR_MODE fifolevel ) ;
6273 USART_MODULE_ID index ,
6274 USART_RECEIVE_INTR_MODE interruptMode ) ;
6307 USART_MODULE_ID index ,
6308 USART_LINECONTROL_MODE dataFlowConfig ) ;
6341 USART_MODULE_ID index ,
6342 USART_HANDSHAKE_MODE handshakeConfig ) ;
6375 USART_MODULE_ID index ,
6406 USART_MODULE_ID index ) ;
6435 USART_MODULE_ID index ) ;
6466 USART_MODULE_ID index ) ;
6497 USART_MODULE_ID index ) ;
6527 USART_MODULE_ID index ) ;
6559 USART_MODULE_ID index ,
6560 USART_OPERATION_MODE operationmode ) ;
6590 USART_MODULE_ID index ) ;
6623 USART_MODULE_ID index ) ;
6652 USART_MODULE_ID index ) ;
6682 USART_MODULE_ID index ) ;
6718 USART_MODULE_ID index ) ;
6769 USART_MODULE_ID index ,
6772 bool wakeFromSleep ,
6817 USART_MODULE_ID index ,
6818 USART_RECEIVE_INTR_MODE receiveInterruptMode ,
6819 USART_TRANSMIT_INTR_MODE transmitInterruptMode ,
6820 USART_OPERATION_MODE operationMode ) ;
6866 USART_MODULE_ID index ,
6867 uint32_t systemClock ,
6913 USART_MODULE_ID index ) ;
6934 USART_MODULE_ID index ) ;
6955 USART_MODULE_ID index ) ;
6989 USART_MODULE_ID index ) ;
7016 USART_MODULE_ID index ) ;
7042 USART_MODULE_ID index ) ;
7069 USART_MODULE_ID index ) ;
7095 USART_MODULE_ID index ) ;
7120 USART_MODULE_ID index ) ;
7146 USART_MODULE_ID index ) ;
7171 USART_MODULE_ID index ) ;
7197 USART_MODULE_ID index ) ;
7222 USART_MODULE_ID index ) ;
7248 USART_MODULE_ID index ) ;
7275 USART_MODULE_ID index ) ;
7301 USART_MODULE_ID index ) ;
7327 USART_MODULE_ID index ) ;
7354 USART_MODULE_ID index ) ;
7381 USART_MODULE_ID index ) ;
7408 USART_MODULE_ID index ) ;
7434 USART_MODULE_ID index ) ;
7459 USART_MODULE_ID index ) ;
7485 USART_MODULE_ID index ) ;
7512 USART_MODULE_ID index ) ;
7538 USART_MODULE_ID index ) ;
7564 USART_MODULE_ID index ) ;
7589 USART_MODULE_ID index ) ;
7614 USART_MODULE_ID index ) ;
7639 USART_MODULE_ID index ) ;
7665 USART_MODULE_ID index ) ;
7690 USART_MODULE_ID index ) ;
7716 USART_MODULE_ID index ) ;
7742 USART_MODULE_ID index ) ;
7767 USART_MODULE_ID index ) ;
7793 USART_MODULE_ID index ) ;
7818 USART_MODULE_ID index ) ;
7843 USART_MODULE_ID index ) ;
7870 USART_MODULE_ID index ) ;
7895 USART_MODULE_ID index ) ;
7921 USART_MODULE_ID index ) ;
7986 #include "system/common/sys_common.h" 7987 #include "system/common/sys_module.h" 7999 #include "system/int/sys_int.h" 8071 #ifndef _SYS_DMA_DEFINITIONS_H 8072 #define _SYS_DMA_DEFINITIONS_H 8078 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 8079 #include "system/common/sys_common.h" 8080 #include "system/common/sys_module.h" 8150 #ifndef _PLIB_DMA_PROCESSOR_H 8151 #define _PLIB_DMA_PROCESSOR_H 8152 #error "Can't find header" 8196 DMA_MODULE_ID index ,
8197 DMA_CHANNEL channel ) ;
8231 DMA_MODULE_ID index ,
8232 DMA_CHANNEL channel ,
8233 DMA_CHANNEL_COLLISION collisonType ) ;
8265 DMA_MODULE_ID index ,
8266 DMA_CHANNEL channel ) ;
8298 DMA_MODULE_ID index ,
8299 DMA_CHANNEL channel ) ;
8337 DMA_MODULE_ID index ,
8338 DMA_CHANNEL channel ,
8339 DMA_CHANNEL_PRIORITY channelPriority ) ;
8368 DMA_CHANNEL_PRIORITY
8370 DMA_MODULE_ID index ,
8371 DMA_CHANNEL channel ) ;
8399 DMA_MODULE_ID index ,
8400 DMA_CHANNEL_PRIORITY channelPriority ) ;
8425 DMA_CHANNEL_PRIORITY
8427 DMA_MODULE_ID index ) ;
8457 DMA_MODULE_ID index ,
8458 DMA_CHANNEL channel ) ;
8489 DMA_MODULE_ID index ,
8490 DMA_CHANNEL channel ) ;
8519 DMA_MODULE_ID index ,
8520 DMA_CHANNEL channel ) ;
8549 DMA_MODULE_ID index ,
8550 DMA_CHANNEL channel ) ;
8581 DMA_MODULE_ID index ,
8582 DMA_CHANNEL channel ) ;
8611 DMA_MODULE_ID index ,
8612 DMA_CHANNEL channel ) ;
8643 DMA_MODULE_ID index ,
8644 DMA_CHANNEL channel ) ;
8675 DMA_MODULE_ID index ,
8676 DMA_CHANNEL channel ) ;
8705 DMA_MODULE_ID index ,
8706 DMA_CHANNEL channel ) ;
8737 DMA_MODULE_ID index ,
8738 DMA_CHANNEL channel ) ;
8767 DMA_MODULE_ID index ,
8768 DMA_CHANNEL channel ) ;
8798 DMA_MODULE_ID index ,
8799 DMA_CHANNEL channel ) ;
8829 DMA_MODULE_ID index ,
8830 DMA_CHANNEL channel ) ;
8860 DMA_MODULE_ID index ,
8861 DMA_CHANNEL channel ) ;
8891 DMA_MODULE_ID index ,
8892 DMA_CHANNEL channel ) ;
8923 DMA_MODULE_ID index ,
8924 DMA_CHANNEL channel ) ;
8955 DMA_MODULE_ID index ,
8956 DMA_CHANNEL channel ,
8957 DMA_CHANNEL_TRANSFER_DIRECTION chTransferDirection ) ;
8986 DMA_CHANNEL_TRANSFER_DIRECTION
8988 DMA_MODULE_ID index ,
8989 DMA_CHANNEL channel ) ;
9025 DMA_MODULE_ID index ,
9026 DMA_CHANNEL channel ,
9028 DMA_ADDRESS_OFFSET_TYPE offset ) ;
9061 DMA_MODULE_ID index ,
9062 DMA_CHANNEL channel ,
9063 DMA_ADDRESS_OFFSET_TYPE offset ) ;
9094 DMA_MODULE_ID index ,
9095 DMA_CHANNEL channel ,
9096 uint16_t peripheraladdress ) ;
9124 DMA_MODULE_ID index ,
9125 DMA_CHANNEL channel ) ;
9156 DMA_MODULE_ID index ,
9157 DMA_CHANNEL channel ,
9158 uint16_t transferCount ) ;
9186 DMA_MODULE_ID index ,
9187 DMA_CHANNEL channel ) ;
9220 DMA_MODULE_ID index ,
9221 DMA_CHANNEL channel ,
9222 DMA_SOURCE_ADDRESSING_MODE sourceAddressMode ) ;
9250 DMA_SOURCE_ADDRESSING_MODE
9252 DMA_MODULE_ID index ,
9253 DMA_CHANNEL channel ) ;
9286 DMA_MODULE_ID index ,
9287 DMA_CHANNEL channel ,
9288 DMA_DESTINATION_ADDRESSING_MODE destinationAddressMode ) ;
9317 DMA_DESTINATION_ADDRESSING_MODE
9319 DMA_MODULE_ID index ,
9320 DMA_CHANNEL channel ) ;
9353 DMA_MODULE_ID index ,
9354 DMA_CHANNEL channel ,
9355 DMA_CHANNEL_ADDRESSING_MODE channelAddressMode ) ;
9383 DMA_CHANNEL_ADDRESSING_MODE
9385 DMA_MODULE_ID index ,
9386 DMA_CHANNEL channel ) ;
9424 DMA_MODULE_ID index ,
9425 DMA_CHANNEL channel ,
9426 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9462 DMA_MODULE_ID index ,
9463 DMA_CHANNEL channel ,
9464 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9499 DMA_MODULE_ID index ,
9500 DMA_CHANNEL channel ,
9501 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9530 DMA_CHANNEL_INT_SOURCE
9532 DMA_MODULE_ID index ,
9533 DMA_CHANNEL channel ) ;
9568 DMA_MODULE_ID index ,
9569 DMA_CHANNEL channel ,
9570 DMA_TRIGGER_SOURCE IRQnum ) ;
9605 DMA_MODULE_ID index ,
9606 DMA_CHANNEL channel ,
9607 DMA_TRIGGER_SOURCE IRQ ) ;
9638 DMA_MODULE_ID index ,
9639 DMA_CHANNEL channel ,
9640 DMA_CHANNEL_DATA_SIZE channelDataSize ) ;
9667 DMA_CHANNEL_DATA_SIZE
9669 DMA_MODULE_ID index ,
9670 DMA_CHANNEL channel ) ;
9704 DMA_MODULE_ID index ,
9705 DMA_CHANNEL channel ,
9706 DMA_TRANSFER_MODE channeltransferMode ) ;
9738 DMA_MODULE_ID index ,
9739 DMA_CHANNEL channel ) ;
9768 DMA_MODULE_ID index ,
9769 DMA_CHANNEL channel ) ;
9799 DMA_MODULE_ID index ,
9800 DMA_CHANNEL channel ) ;
9829 DMA_MODULE_ID index ,
9830 DMA_CHANNEL channel ) ;
9858 DMA_MODULE_ID index ,
9859 DMA_CHANNEL channel ) ;
9889 DMA_MODULE_ID index ,
9890 DMA_CHANNEL channel ) ;
9917 DMA_MODULE_ID index ,
9918 DMA_CHANNEL channel ) ;
9954 DMA_MODULE_ID index ,
9955 DMA_CHANNEL channel ) ;
9986 DMA_MODULE_ID index ,
9987 DMA_CHANNEL channel ) ;
10020 DMA_MODULE_ID index ) ;
10049 DMA_MODULE_ID index ) ;
10079 DMA_MODULE_ID index ) ;
10108 DMA_MODULE_ID index ) ;
10137 DMA_MODULE_ID index ) ;
10167 DMA_MODULE_ID index ) ;
10195 DMA_MODULE_ID index ) ;
10223 DMA_MODULE_ID index ) ;
10251 DMA_MODULE_ID index ) ;
10280 DMA_MODULE_ID index ) ;
10308 DMA_MODULE_ID index ) ;
10342 DMA_MODULE_ID index ) ;
10372 DMA_MODULE_ID index ) ;
10402 DMA_MODULE_ID index ) ;
10431 DMA_MODULE_ID index ) ;
10466 DMA_MODULE_ID index ,
10467 DMA_CHANNEL channel ) ;
10496 DMA_MODULE_ID index ) ;
10528 DMA_MODULE_ID index ,
10529 DMA_CRC_TYPE CRCType ) ;
10560 DMA_MODULE_ID index ) ;
10590 DMA_MODULE_ID index ) ;
10620 DMA_MODULE_ID index ) ;
10650 DMA_MODULE_ID index ) ;
10679 DMA_MODULE_ID index ) ;
10709 DMA_MODULE_ID index ) ;
10738 DMA_MODULE_ID index ) ;
10768 DMA_MODULE_ID index ,
10769 uint8_t polyLength ) ;
10798 DMA_MODULE_ID index ) ;
10827 DMA_MODULE_ID index ,
10828 DMA_CRC_BIT_ORDER bitOrder ) ;
10859 DMA_MODULE_ID index ) ;
10888 DMA_MODULE_ID index ) ;
10918 DMA_MODULE_ID index ,
10919 DMA_CRC_BYTE_ORDER byteOrder ) ;
10948 DMA_MODULE_ID index ) ;
10979 DMA_MODULE_ID index ) ;
11011 DMA_MODULE_ID index ,
11012 uint32_t DMACRCdata ) ;
11043 DMA_MODULE_ID index ) ;
11076 DMA_MODULE_ID index ,
11077 uint32_t DMACRCXOREnableMask ) ;
11115 DMA_MODULE_ID index ,
11116 DMA_CHANNEL dmaChannel ) ;
11153 DMA_MODULE_ID index ,
11154 DMA_CHANNEL dmaChannel ,
11155 uint32_t sourceStartAddress ) ;
11189 DMA_MODULE_ID index ,
11190 DMA_CHANNEL dmaChannel ) ;
11228 DMA_MODULE_ID index ,
11229 DMA_CHANNEL dmaChannel ,
11230 uint32_t destinationStartAddress ) ;
11270 DMA_MODULE_ID index ,
11271 DMA_CHANNEL dmaChannel ) ;
11310 DMA_MODULE_ID index ,
11311 DMA_CHANNEL dmaChannel ,
11312 uint16_t sourceSize ) ;
11347 DMA_MODULE_ID index ,
11348 DMA_CHANNEL dmaChannel ) ;
11385 DMA_MODULE_ID index ,
11386 DMA_CHANNEL dmaChannel ,
11387 uint16_t destinationSize ) ;
11421 DMA_MODULE_ID index ,
11422 DMA_CHANNEL dmaChannel ) ;
11457 DMA_MODULE_ID index ,
11458 DMA_CHANNEL dmaChannel ) ;
11493 DMA_MODULE_ID index ,
11494 DMA_CHANNEL dmaChannel ) ;
11531 DMA_MODULE_ID index ,
11532 DMA_CHANNEL dmaChannel ,
11533 uint16_t CellSize ) ;
11567 DMA_MODULE_ID index ,
11568 DMA_CHANNEL dmaChannel ) ;
11605 DMA_MODULE_ID index ,
11606 DMA_CHANNEL dmaChannel ) ;
11645 DMA_MODULE_ID index ,
11646 DMA_CHANNEL dmaChannel ,
11647 uint16_t patternData ) ;
11691 DMA_MODULE_ID index ,
11692 DMA_CHANNEL dmaChannel ,
11693 DMA_INT_TYPE dmaINTSource ) ;
11728 DMA_MODULE_ID index ,
11729 DMA_CHANNEL dmaChannel ,
11730 DMA_INT_TYPE dmaINTSource ) ;
11766 DMA_MODULE_ID index ,
11767 DMA_CHANNEL dmaChannel ,
11768 DMA_INT_TYPE dmaINTSource ) ;
11802 DMA_MODULE_ID index ,
11803 DMA_CHANNEL dmaChannel ,
11804 DMA_INT_TYPE dmaINTSource ) ;
11838 DMA_MODULE_ID index ,
11839 DMA_CHANNEL dmaChannel ,
11840 DMA_INT_TYPE dmaINTSource ) ;
11878 DMA_MODULE_ID index ,
11879 DMA_CHANNEL dmaChannel ,
11880 DMA_INT_TYPE dmaINTSource ) ;
11913 DMA_MODULE_ID index ,
11914 DMA_CHANNEL dmaChannel ,
11915 DMA_PATTERN_LENGTH patternLen ) ;
11948 DMA_MODULE_ID index ,
11949 DMA_CHANNEL dmaChannel ) ;
11979 DMA_MODULE_ID index ,
11980 DMA_CHANNEL channel ) ;
12013 DMA_MODULE_ID index ,
12014 DMA_CHANNEL channel ) ;
12044 DMA_MODULE_ID index ,
12045 DMA_CHANNEL channel ) ;
12077 DMA_MODULE_ID index ,
12078 DMA_CHANNEL channel ,
12079 uint8_t pattern ) ;
12110 DMA_MODULE_ID index ,
12111 DMA_CHANNEL channel ) ;
12143 DMA_MODULE_ID index ) ;
12168 DMA_MODULE_ID index ) ;
12192 DMA_MODULE_ID index ) ;
12217 DMA_MODULE_ID index ) ;
12240 DMA_MODULE_ID index ) ;
12264 DMA_MODULE_ID index ) ;
12287 DMA_MODULE_ID index ) ;
12311 DMA_MODULE_ID index ) ;
12335 DMA_MODULE_ID index ) ;
12360 DMA_MODULE_ID index ) ;
12384 DMA_MODULE_ID index ) ;
12408 DMA_MODULE_ID index ) ;
12431 DMA_MODULE_ID index ) ;
12455 DMA_MODULE_ID index ) ;
12479 DMA_MODULE_ID index ) ;
12503 DMA_MODULE_ID index ) ;
12527 DMA_MODULE_ID index ) ;
12551 DMA_MODULE_ID index ) ;
12574 DMA_MODULE_ID index ) ;
12599 DMA_MODULE_ID index ) ;
12624 DMA_MODULE_ID index ) ;
12648 DMA_MODULE_ID index ) ;
12673 DMA_MODULE_ID index ) ;
12697 DMA_MODULE_ID index ) ;
12721 DMA_MODULE_ID index ) ;
12747 DMA_MODULE_ID index ) ;
12772 DMA_MODULE_ID index ) ;
12796 DMA_MODULE_ID index ) ;
12821 DMA_MODULE_ID index ) ;
12844 DMA_MODULE_ID index ) ;
12867 DMA_MODULE_ID index ) ;
12890 DMA_MODULE_ID index ) ;
12913 DMA_MODULE_ID index ) ;
12938 DMA_MODULE_ID index ) ;
12963 DMA_MODULE_ID index ) ;
12987 DMA_MODULE_ID index ) ;
13012 DMA_MODULE_ID index ) ;
13036 DMA_MODULE_ID index ) ;
13060 DMA_MODULE_ID index ) ;
13083 DMA_MODULE_ID index ) ;
13106 DMA_MODULE_ID index ) ;
13130 DMA_MODULE_ID index ) ;
13154 DMA_MODULE_ID index ) ;
13178 DMA_MODULE_ID index ) ;
13205 #define DMA_CHANNEL_NONE ( ( DMA_CHANNEL ) - 1 ) 13218 #define DMA_CHANNEL_ANY ( ( DMA_CHANNEL ) - 2 ) 13231 #define SYS_DMA_CHANNEL_COUNT DMA_NUMBER_OF_CHANNELS 13261 #define SYS_DMA_CHANNEL_HANDLE_INVALID ( ( SYS_DMA_CHANNEL_HANDLE ) ( - 1 ) ) 13582 SYS_MODULE_OBJ
object ,
13583 DMA_CHANNEL activeChannel ) ;
13586 #define SYS_DMA_TasksISR( object , activeChannel ) SYS_DMA_Tasks ( object , activeChannel ) 13631 uintptr_t contextHandle ) ;
13677 const SYS_MODULE_INIT *
const init ) ;
13728 DMA_CHANNEL channel ) ;
13814 DMA_TRIGGER_SOURCE eventSrc ) ;
13892 DMA_PATTERN_LENGTH length ,
13894 uint8_t ignorePattern ) ;
14147 const void * srcAddr ,
14149 const void * destAddr ,
14151 size_t cellSize ) ;
14248 const void * srcAddr ,
14250 const void * destAddr ,
14252 size_t cellSize ) ;
14448 const uintptr_t contextHandle ) ;
14744 DMA_TRIGGER_SOURCE eventSrc ) ;
14923 SYS_MODULE_OBJ
object ,
14924 DMA_CHANNEL activeChannel ) ;
14934 SYS_MODULE_OBJ
object ) ;
14944 SYS_MODULE_OBJ
object ,
14945 DMA_CHANNEL activeChannel ) ;
14972 #define DRV_USART_INDEX_0 0 14973 #define DRV_USART_INDEX_1 1 14974 #define DRV_USART_INDEX_2 2 14975 #define DRV_USART_INDEX_3 3 14976 #define DRV_USART_INDEX_4 4 14977 #define DRV_USART_INDEX_5 5 14991 #define DRV_USART_COUNT USART_NUMBER_OF_MODULES 15002 #define DRV_USART_WRITE_ERROR ( ( uint32_t ) ( - 1 ) ) 15013 #define DRV_USART_READ_ERROR ( ( uint32_t ) ( - 1 ) ) 15047 #define DRV_USART_BUFFER_HANDLE_INVALID ( ( DRV_USART_BUFFER_HANDLE ) ( - 1 ) ) 15198 uintptr_t context ) ;
15246 USART_HANDSHAKE_MODE_FLOW_CONTROL
15250 USART_HANDSHAKE_MODE_SIMPLEX
15412 } AddressedModeInit ;
15437 = USART_ERROR_PARITY
15442 = USART_ERROR_FRAMING
15447 = USART_ERROR_RECEIVER_OVERRUN
15689 const SYS_MODULE_INDEX index ,
15690 const SYS_MODULE_INIT *
const init ) ;
15728 SYS_MODULE_OBJ
object ) ;
15766 SYS_MODULE_OBJ
object ) ;
15807 SYS_MODULE_OBJ
object ) ;
15848 SYS_MODULE_OBJ
object ) ;
15889 SYS_MODULE_OBJ
object ) ;
15968 const SYS_MODULE_INDEX index ,
16152 const size_t size ) ;
16345 const size_t size ) ;
16433 const uintptr_t context ) ;
16700 const size_t numbytes ) ;
16768 const size_t numbytes ) ;
16905 const uint8_t byte ) ;
17123 const SYS_MODULE_INDEX index ,
17176 const SYS_MODULE_INDEX index ,
17225 const SYS_MODULE_INDEX index ,
17440 #ifndef _DRV_USART_FEATURE_MAPPING_H 17441 #define _DRV_USART_FEATURE_MAPPING_H 17450 #define _DRV_USART_InterruptSourceIsEnabled( source ) false 17451 #define _DRV_USART_InterruptSourceEnable( source ) 17452 #define _DRV_USART_InterruptSourceDisable( source ) false 17453 #define _DRV_USART_InterruptSourceStatusClear( source ) SYS_INT_SourceStatusClear ( source ) 17454 #define _DRV_USART_SEM_POST( x ) OSAL_SEM_Post ( x ) 17455 #define _DRV_USART_TAKE_MUTEX( x , y ) OSAL_MUTEX_Lock ( x , y ) 17456 #define _DRV_USART_RELEASE_MUTEX( x ) OSAL_MUTEX_Unlock ( x ) 17457 #define _SYS_DMA_ChannelForceStart( channelHandle ) SYS_DMA_ChannelForceStart ( channelHandle ) 17460 #define _DRV_USART_ALWAYS_NON_BLOCKING ( DRV_IO_INTENT_NONBLOCKING ) 17469 #define _DRV_USART_TRANSMIT_BUFFER_QUEUE_TASKS( x ) _DRV_USART_ByteTransmitTasks ( x ) 17470 #define _DRV_USART_RECEIVE_BUFFER_QUEUE_TASKS( x ) _DRV_USART_ByteReceiveTasks ( x ) 17471 #define _DRV_USART_ERROR_TASKS( x ) _DRV_USART_ByteErrorTasks ( x ) 17472 #define _DRV_USART_CLIENT_BUFFER_QUEUE_OBJECTS_REMOVE( x ) true 17473 #define _DRV_USART_ByteModelInterruptSourceEnable( source ) 17486 #include "system/clk/sys_clk.h" 17487 #include "system/int/sys_int.h" 17525 #ifndef _SYS_DEBUG_H 17526 #define _SYS_DEBUG_H 17527 #include "C:\microchip\harmony\v2_06\framework\system\system.h" 17530 #define SYS_DEBUG_BUFFER_DMA_READY 17580 #define SYS_DEBUG_INDEX_0 0 17648 const SYS_MODULE_INDEX index ,
17649 const SYS_MODULE_INIT *
const init ) ;
17689 SYS_MODULE_OBJ
object ,
17690 const SYS_MODULE_INIT *
const init ) ;
17720 SYS_MODULE_OBJ
object ) ;
17753 SYS_MODULE_OBJ
object ) ;
17797 SYS_MODULE_OBJ
object ) ;
17840 const char * message ) ;
17890 const char * format ,
17980 #define _SYS_DEBUG_MESSAGE( level , message ) do { if ( ( level ) <= SYS_DEBUG_ErrorLevelGet ( ) ) SYS_DEBUG_Message ( message ) ; } while ( 0 ) 18024 #define _SYS_DEBUG_PRINT( level , format ,... ) do { if ( ( level ) <= SYS_DEBUG_ErrorLevelGet ( ) ) SYS_DEBUG_Print ( format , ## __VA_ARGS__ ) ; } while ( 0 ) 18067 #define SYS_MESSAGE( message ) 18100 #define SYS_DEBUG_MESSAGE( level , message ) 18147 #define SYS_PRINT( fmt ,... ) 18195 #define SYS_DEBUG_PRINT( level , fmt ,... ) 18220 #define SYS_DEBUG_BreakPoint( ) 18229 #define SYS_DEBUG( level , message ) SYS_DEBUG_MESSAGE ( level , message ) 18230 #define SYS_ERROR( level , fmt ,... ) SYS_DEBUG_PRINT ( level , fmt , ## __VA_ARGS__ ) 18231 #define SYS_ERROR_PRINT( level , fmt ,... ) SYS_DEBUG_PRINT ( level , fmt , ## __VA_ARGS__ ) 18248 #define _DRV_USART_RX_DEPTH 9 18314 const SYS_MODULE_INDEX index ,
18339 const uint8_t byte ) ;
18410 #ifndef _SYS_PORTS_H 18411 #define _SYS_PORTS_H 18450 #ifndef _SYS_PORTS_DEFINITIONS_H 18451 #define _SYS_PORTS_DEFINITIONS_H 18457 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 18458 #include "system/common/sys_common.h" 18459 #include "system/common/sys_module.h" 18496 #ifndef _PLIB_PORTS_H 18497 #define _PLIB_PORTS_H 18498 #include <stdint.h> 18499 #include <stddef.h> 18564 #ifndef _PLIB_PORTS_PROCESSOR_H 18565 #define _PLIB_PORTS_PROCESSOR_H 18566 #error "Can't find header" 18616 PORTS_MODULE_ID index ,
18617 PORTS_REMAP_INPUT_FUNCTION inputFunction ,
18618 PORTS_REMAP_INPUT_PIN remapInputPin ) ;
18661 PORTS_MODULE_ID index ,
18662 PORTS_REMAP_OUTPUT_FUNCTION outputFunction ,
18663 PORTS_REMAP_OUTPUT_PIN remapOutputPin ) ;
18698 PORTS_MODULE_ID index ,
18699 PORTS_ANALOG_PIN pin ,
18700 PORTS_PIN_MODE mode ) ;
18740 PORTS_MODULE_ID index ,
18741 PORTS_CHANNEL channel ,
18742 PORTS_BIT_POS bitPos ,
18743 PORTS_PIN_MODE mode ) ;
18778 PORTS_MODULE_ID index ,
18779 PORTS_CHANNEL channel ,
18780 PORTS_BIT_POS bitPos ) ;
18814 PORTS_MODULE_ID index ,
18815 PORTS_CHANNEL channel ,
18816 PORTS_BIT_POS bitPos ) ;
18853 PORTS_MODULE_ID index ,
18854 PORTS_CHANNEL channel ,
18855 PORTS_BIT_POS bitPos ) ;
18896 PORTS_MODULE_ID index ,
18897 PORTS_CHANNEL channel ,
18898 PORTS_BIT_POS bitPos ) ;
18937 PORTS_MODULE_ID index ,
18938 PORTS_CHANNEL channel ,
18939 PORTS_BIT_POS bitPos ) ;
18977 PORTS_MODULE_ID index ,
18978 PORTS_CHANNEL channel ,
18979 PORTS_BIT_POS bitPos ) ;
19014 PORTS_MODULE_ID index ,
19015 PORTS_CHANNEL channel ) ;
19050 PORTS_MODULE_ID index ,
19051 PORTS_CHANNEL channel ) ;
19088 PORTS_MODULE_ID index ,
19089 PORTS_CHANNEL channel ) ;
19126 PORTS_MODULE_ID index ,
19127 PORTS_CHANNEL channel ) ;
19164 PORTS_MODULE_ID index ,
19165 PORTS_CHANNEL channel ,
19166 PORTS_BIT_POS bitPos ) ;
19203 PORTS_MODULE_ID index ,
19204 PORTS_CHANNEL channel ,
19205 PORTS_BIT_POS bitPos ) ;
19243 PORTS_MODULE_ID index ,
19244 PORTS_CHANNEL channel ,
19245 PORTS_BIT_POS bitPos ) ;
19282 PORTS_MODULE_ID index ,
19283 PORTS_CHANNEL channel ,
19284 PORTS_BIT_POS bitPos ,
19319 PORTS_MODULE_ID index ,
19320 PORTS_CHANNEL channel ,
19321 PORTS_BIT_POS bitPos ) ;
19355 PORTS_MODULE_ID index ,
19356 PORTS_CHANNEL channel ,
19357 PORTS_BIT_POS bitPos ) ;
19391 PORTS_MODULE_ID index ,
19392 PORTS_CHANNEL channel ,
19393 PORTS_BIT_POS bitPos ) ;
19428 PORTS_MODULE_ID index ,
19429 PORTS_CHANNEL channel ,
19430 PORTS_BIT_POS bitPos ) ;
19465 PORTS_MODULE_ID index ,
19466 PORTS_CHANNEL channel ,
19467 PORTS_BIT_POS bitPos ) ;
19501 PORTS_MODULE_ID index ,
19502 PORTS_CHANNEL channel ,
19503 PORTS_BIT_POS bitPos ) ;
19537 PORTS_MODULE_ID index ,
19538 PORTS_CHANNEL channel ,
19539 PORTS_BIT_POS bitPos ) ;
19577 PORTS_MODULE_ID index ,
19578 PORTS_CHANNEL channel ) ;
19612 PORTS_MODULE_ID index ,
19613 PORTS_CHANNEL channel ) ;
19647 PORTS_MODULE_ID index ,
19648 PORTS_CHANNEL channel ,
19691 PORTS_MODULE_ID index ,
19692 PORTS_CHANNEL channel ,
19728 PORTS_MODULE_ID index ,
19729 PORTS_CHANNEL channel ,
19764 PORTS_MODULE_ID index ,
19765 PORTS_CHANNEL channel ,
19801 PORTS_MODULE_ID index ,
19802 PORTS_CHANNEL channel ,
19837 PORTS_MODULE_ID index ,
19838 PORTS_CHANNEL channel ,
19871 PORTS_MODULE_ID index ,
19872 PORTS_CHANNEL channel ) ;
19906 PORTS_MODULE_ID index ,
19907 PORTS_CHANNEL channel ,
19943 PORTS_MODULE_ID index ,
19944 PORTS_CHANNEL channel ,
19990 PORTS_MODULE_ID index ,
19991 PORTS_CHANNEL channel ,
19993 PORTS_PIN_MODE mode ) ;
20035 PORTS_MODULE_ID index ,
20036 PORTS_CHANNEL channel ,
20079 PORTS_MODULE_ID index ,
20080 PORTS_CHANNEL channel ,
20120 PORTS_MODULE_ID index ,
20121 PORTS_CHANNEL channel ,
20161 PORTS_MODULE_ID index ,
20162 PORTS_CHANNEL channel ,
20206 PORTS_MODULE_ID index ,
20207 PORTS_CHANNEL channel ,
20251 PORTS_MODULE_ID index ,
20252 PORTS_CHANNEL channel ,
20298 PORTS_MODULE_ID index ,
20299 PORTS_AN_PIN anPins ,
20300 PORTS_PIN_MODE mode ) ;
20343 PORTS_MODULE_ID index ,
20344 PORTS_CN_PIN cnPins ) ;
20388 PORTS_MODULE_ID index ,
20389 PORTS_CN_PIN cnPins ) ;
20432 PORTS_MODULE_ID index ,
20433 PORTS_CN_PIN cnPins ) ;
20476 PORTS_MODULE_ID index ,
20477 PORTS_CN_PIN cnPins ) ;
20511 PORTS_MODULE_ID index ) ;
20544 PORTS_MODULE_ID index ) ;
20580 PORTS_MODULE_ID index ,
20581 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20617 PORTS_MODULE_ID index ,
20618 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20655 PORTS_MODULE_ID index ) ;
20689 PORTS_MODULE_ID index ) ;
20725 PORTS_MODULE_ID index ,
20726 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20762 PORTS_MODULE_ID index ,
20763 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20808 PORTS_MODULE_ID index ,
20809 PORTS_CHANNEL channel ,
20811 PORTS_PIN_SLEW_RATE slewRate ) ;
20848 PORTS_PIN_SLEW_RATE
20850 PORTS_MODULE_ID index ,
20851 PORTS_CHANNEL channel ,
20852 PORTS_BIT_POS bitPos ) ;
20891 PORTS_MODULE_ID index ,
20892 PORTS_CHANNEL channel ,
20893 PORTS_CHANGE_NOTICE_METHOD changeNoticeMethod ) ;
20926 PORTS_CHANGE_NOTICE_METHOD
20928 PORTS_MODULE_ID index ,
20929 PORTS_CHANNEL channel ) ;
20977 PORTS_MODULE_ID index ,
20978 PORTS_CHANNEL channel ,
21028 PORTS_MODULE_ID index ,
21029 PORTS_CHANNEL channel ,
21077 PORTS_MODULE_ID index ,
21078 PORTS_CHANNEL channel ,
21079 PORTS_BIT_POS bitPos ,
21080 PORTS_CHANGE_NOTICE_EDGE cnEdgeType ) ;
21123 PORTS_MODULE_ID index ,
21124 PORTS_CHANNEL channel ,
21125 PORTS_BIT_POS bitPos ) ;
21156 PORTS_MODULE_ID index ) ;
21180 PORTS_MODULE_ID index ) ;
21204 PORTS_MODULE_ID index ) ;
21228 PORTS_MODULE_ID index ) ;
21253 PORTS_MODULE_ID index ) ;
21278 PORTS_MODULE_ID index ) ;
21309 PORTS_MODULE_ID index ) ;
21337 PORTS_MODULE_ID index ) ;
21364 PORTS_MODULE_ID index ) ;
21389 PORTS_MODULE_ID index ) ;
21416 PORTS_MODULE_ID index ) ;
21441 PORTS_MODULE_ID index ) ;
21468 PORTS_MODULE_ID index ) ;
21493 PORTS_MODULE_ID index ) ;
21521 PORTS_MODULE_ID index ) ;
21549 PORTS_MODULE_ID index ) ;
21577 PORTS_MODULE_ID index ) ;
21603 PORTS_MODULE_ID index ) ;
21629 PORTS_MODULE_ID index ) ;
21655 PORTS_MODULE_ID index ) ;
21680 PORTS_MODULE_ID index ) ;
21706 PORTS_MODULE_ID index ) ;
21733 PORTS_MODULE_ID index ) ;
21758 PORTS_MODULE_ID index ) ;
21793 #ifndef _PLIB_PORTS_COMPATIBILITY_H 21794 #define _PLIB_PORTS_COMPATIBILITY_H 21795 #include <stdint.h> 21796 #include <stddef.h> 21831 #define PLIB_PORTS_ChangeNoticePerPortHasOccured PLIB_PORTS_ChangeNoticePerPortHasOccurred 21848 #include "system/int/sys_int.h" 21982 PORTS_MODULE_ID index ,
21983 PORTS_CHANNEL channel ) ;
22015 PORTS_MODULE_ID index ,
22016 PORTS_CHANNEL channel ,
22046 PORTS_MODULE_ID index ,
22047 PORTS_CHANNEL channel ) ;
22085 PORTS_MODULE_ID index ,
22086 PORTS_CHANNEL channel ,
22120 PORTS_MODULE_ID index ,
22121 PORTS_CHANNEL channel ,
22158 PORTS_MODULE_ID index ,
22160 PORTS_CHANNEL channel ,
22190 PORTS_MODULE_ID index ,
22191 PORTS_CHANNEL channel ) ;
22222 PORTS_MODULE_ID index ,
22223 PORTS_CHANNEL channel ,
22255 PORTS_MODULE_ID index ,
22256 PORTS_CHANNEL channel ,
22288 PORTS_MODULE_ID index ,
22289 PORTS_CHANNEL channel ,
22323 PORTS_MODULE_ID index ,
22324 PORTS_CHANNEL channel ) ;
22364 PORTS_MODULE_ID index ,
22365 PORTS_REMAP_INPUT_FUNCTION
function ,
22366 PORTS_REMAP_INPUT_PIN remapPin ) ;
22401 PORTS_MODULE_ID index ,
22402 PORTS_REMAP_OUTPUT_FUNCTION
function ,
22403 PORTS_REMAP_OUTPUT_PIN remapPin ) ;
22436 PORTS_MODULE_ID index ) ;
22464 PORTS_MODULE_ID index ) ;
22498 PORTS_MODULE_ID index ,
22499 PORTS_CHANGE_NOTICE_PIN pinNum ,
22531 PORTS_MODULE_ID index ,
22532 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22561 PORTS_MODULE_ID index ) ;
22590 PORTS_MODULE_ID index ) ;
22621 PORTS_MODULE_ID index ,
22622 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22653 PORTS_MODULE_ID index ,
22654 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22693 PORTS_MODULE_ID index ,
22694 PORTS_ANALOG_PIN pin ,
22695 PORTS_PIN_MODE mode ) ;
22732 PORTS_MODULE_ID index ,
22733 PORTS_CHANNEL channel ,
22734 PORTS_BIT_POS bitPos ,
22769 PORTS_MODULE_ID index ,
22770 PORTS_CHANNEL channel ,
22771 PORTS_BIT_POS bitPos ) ;
22804 PORTS_MODULE_ID index ,
22805 PORTS_CHANNEL channel ,
22806 PORTS_BIT_POS bitPos ) ;
22839 PORTS_MODULE_ID index ,
22840 PORTS_CHANNEL channel ,
22841 PORTS_BIT_POS bitPos ) ;
22874 PORTS_MODULE_ID index ,
22875 PORTS_CHANNEL channel ,
22876 PORTS_BIT_POS bitPos ) ;
22909 PORTS_MODULE_ID index ,
22910 PORTS_CHANNEL channel ,
22911 PORTS_BIT_POS bitPos ) ;
22948 PORTS_MODULE_ID index ,
22950 PORTS_CHANNEL channel ,
22951 PORTS_BIT_POS bitPos ) ;
22984 PORTS_MODULE_ID index ,
22985 PORTS_CHANNEL channel ,
22986 PORTS_BIT_POS bitPos ) ;
23019 PORTS_MODULE_ID index ,
23020 PORTS_CHANNEL channel ,
23021 PORTS_BIT_POS bitPos ) ;
23054 PORTS_MODULE_ID index ,
23055 PORTS_CHANNEL channel ,
23056 PORTS_BIT_POS bitPos ) ;
23089 PORTS_MODULE_ID index ,
23090 PORTS_CHANNEL channel ,
23091 PORTS_BIT_POS bitPos ) ;
23124 PORTS_MODULE_ID index ,
23125 PORTS_CHANNEL channel ,
23126 PORTS_BIT_POS bitPos ) ;
23159 PORTS_MODULE_ID index ,
23160 PORTS_CHANNEL channel ,
23161 PORTS_BIT_POS bitPos ) ;
23194 PORTS_MODULE_ID index ,
23195 PORTS_CHANNEL channel ,
23196 PORTS_BIT_POS bitPos ,
23279 #ifndef _DRV_SPI_DEFINITIONS_H 23280 #define _DRV_SPI_DEFINITIONS_H 23286 #include <stdint.h> 23287 #include <stdbool.h> 23288 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 23289 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 23325 #ifndef _PLIB_SPI_H 23326 #define _PLIB_SPI_H 23360 #ifndef _PLIB_SPI_PROCESSOR_H 23361 #define _PLIB_SPI_PROCESSOR_H 23362 #error "Can't find header" 23407 SPI_MODULE_ID index ) ;
23437 SPI_MODULE_ID index ) ;
23469 SPI_MODULE_ID index ) ;
23501 SPI_MODULE_ID index ) ;
23535 SPI_MODULE_ID index ) ;
23565 SPI_MODULE_ID index ) ;
23602 SPI_MODULE_ID index ) ;
23641 SPI_MODULE_ID index ) ;
23671 SPI_MODULE_ID index ,
23702 SPI_MODULE_ID index ,
23736 SPI_MODULE_ID index ,
23737 SPI_COMMUNICATION_WIDTH width ) ;
23772 SPI_MODULE_ID index ,
23773 SPI_AUDIO_COMMUNICATION_WIDTH mode ) ;
23805 SPI_MODULE_ID index ,
23806 SPI_INPUT_SAMPLING_PHASE phase ) ;
23838 SPI_MODULE_ID index ,
23839 SPI_OUTPUT_DATA_PHASE phase ) ;
23870 SPI_MODULE_ID index ,
23871 SPI_CLOCK_POLARITY polarity ) ;
23901 SPI_MODULE_ID index ) ;
23931 SPI_MODULE_ID index ) ;
23969 SPI_MODULE_ID index ,
23970 uint32_t clockFrequency ,
23971 uint32_t baudRate ) ;
24002 SPI_MODULE_ID index ) ;
24034 SPI_MODULE_ID index ) ;
24067 SPI_MODULE_ID index ) ;
24100 SPI_MODULE_ID index ) ;
24132 SPI_MODULE_ID index ) ;
24162 SPI_MODULE_ID index ) ;
24193 SPI_MODULE_ID index ) ;
24224 SPI_MODULE_ID index ) ;
24255 SPI_MODULE_ID index ) ;
24287 SPI_MODULE_ID index ,
24288 SPI_FIFO_TYPE type ) ;
24320 SPI_MODULE_ID index ) ;
24352 SPI_MODULE_ID index ) ;
24386 SPI_MODULE_ID index ,
24387 SPI_FIFO_INTERRUPT mode ) ;
24417 SPI_MODULE_ID index ) ;
24447 SPI_MODULE_ID index ) ;
24479 SPI_MODULE_ID index ,
24480 SPI_FRAME_PULSE_DIRECTION direction ) ;
24513 SPI_MODULE_ID index ,
24514 SPI_FRAME_PULSE_POLARITY polarity ) ;
24547 SPI_MODULE_ID index ,
24548 SPI_FRAME_PULSE_EDGE edge ) ;
24581 SPI_MODULE_ID index ,
24582 SPI_FRAME_PULSE_WIDTH width ) ;
24616 SPI_MODULE_ID index ,
24617 SPI_FRAME_SYNC_PULSE pulse ) ;
24649 SPI_MODULE_ID index ) ;
24679 SPI_MODULE_ID index ) ;
24711 SPI_MODULE_ID index ) ;
24741 SPI_MODULE_ID index ) ;
24771 SPI_MODULE_ID index ) ;
24801 SPI_MODULE_ID index ) ;
24832 SPI_MODULE_ID index ,
24864 SPI_MODULE_ID index ,
24896 SPI_MODULE_ID index ,
24919 SPI_MODULE_ID index ) ;
24950 SPI_MODULE_ID index ,
24951 SPI_BAUD_RATE_CLOCK type ) ;
24983 SPI_MODULE_ID index ,
24984 SPI_ERROR_INTERRUPT error ) ;
25016 SPI_MODULE_ID index ,
25017 SPI_ERROR_INTERRUPT error ) ;
25048 SPI_MODULE_ID index ,
25049 SPI_AUDIO_ERROR error ) ;
25080 SPI_MODULE_ID index ,
25081 SPI_AUDIO_ERROR error ) ;
25111 SPI_MODULE_ID index ) ;
25141 SPI_MODULE_ID index ) ;
25173 SPI_MODULE_ID index ,
25174 SPI_AUDIO_TRANSMIT_MODE mode ) ;
25206 SPI_MODULE_ID index ,
25207 SPI_AUDIO_PROTOCOL mode ) ;
25240 SPI_MODULE_ID index ) ;
25266 SPI_MODULE_ID index ) ;
25292 SPI_MODULE_ID index ) ;
25317 SPI_MODULE_ID index ) ;
25342 SPI_MODULE_ID index ) ;
25367 SPI_MODULE_ID index ) ;
25393 SPI_MODULE_ID index ) ;
25418 SPI_MODULE_ID index ) ;
25443 SPI_MODULE_ID index ) ;
25468 SPI_MODULE_ID index ) ;
25493 SPI_MODULE_ID index ) ;
25518 SPI_MODULE_ID index ) ;
25544 SPI_MODULE_ID index ) ;
25569 SPI_MODULE_ID index ) ;
25594 SPI_MODULE_ID index ) ;
25619 SPI_MODULE_ID index ) ;
25645 SPI_MODULE_ID index ) ;
25671 SPI_MODULE_ID index ) ;
25697 SPI_MODULE_ID index ) ;
25721 SPI_MODULE_ID index ) ;
25746 SPI_MODULE_ID index ) ;
25771 SPI_MODULE_ID index ) ;
25796 SPI_MODULE_ID index ) ;
25822 SPI_MODULE_ID index ) ;
25847 SPI_MODULE_ID index ) ;
25872 SPI_MODULE_ID index ) ;
25897 SPI_MODULE_ID index ) ;
25922 SPI_MODULE_ID index ) ;
25947 SPI_MODULE_ID index ) ;
25973 SPI_MODULE_ID index ) ;
26000 SPI_MODULE_ID index ) ;
26025 SPI_MODULE_ID index ) ;
26051 SPI_MODULE_ID index ) ;
26077 SPI_MODULE_ID index ) ;
26103 SPI_MODULE_ID index ) ;
26128 SPI_MODULE_ID index ) ;
26153 SPI_MODULE_ID index ) ;
26179 SPI_MODULE_ID index ) ;
26205 SPI_MODULE_ID index ) ;
26217 #include "system/common/sys_common.h" 26218 #include "system/common/sys_module.h" 26219 #include "system/int/sys_int.h" 26220 #include "system/clk/sys_clk.h" 26221 #include "C:\microchip\harmony\v2_06\framework\system\ports\sys_ports.h" 26259 #define DRV_SPI_BUFFER_HANDLE_INVALID ( ( DRV_SPI_BUFFER_HANDLE ) ( - 1 ) ) 26271 #define DRV_SPI_INDEX_0 0 26272 #define DRV_SPI_INDEX_1 1 26273 #define DRV_SPI_INDEX_2 2 26274 #define DRV_SPI_INDEX_3 3 26275 #define DRV_SPI_INDEX_4 4 26276 #define DRV_SPI_INDEX_5 5 26288 #define DRV_SPI_INDEX_COUNT SPI_NUMBER_OF_MODULES 26730 const SYS_MODULE_INDEX index ,
26731 const SYS_MODULE_INIT *
const init ) ;
26773 SYS_MODULE_OBJ
object ) ;
26822 SYS_MODULE_OBJ
object ) ;
26863 SYS_MODULE_OBJ
object ) ;
26928 const SYS_MODULE_INDEX drvIndex ,
27523 #include "driver/usb/usbhs/drv_usbhs.h" 27552 #include <stdint.h> 27572 uint8_t RevNumber ;
27742 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 28)));
27820 #define qqqbranches 77 27821 #define QQQMAXMCDCSIZE 2 27825 #define ldra_sscanf 27841 #undef qqnull_params 27842 #define qqnull_params void 27844 #define qqzzidfield 1 27850 #define QQQFIXEDSIZE 27870 qqcptr = qqscan_str;
27872 while (qqcptr[0] ==
' ')
27878 if (qqcptr[0] ==
'-')
27884 while ((qqcptr[0] >=
'0') && (qqcptr[0] <=
'9'))
27886 qqvalue = 10 * qqvalue;
27887 qqvalue = qqvalue + (qqcptr[0] -
'0');
27890 qqvalue = qqisign * qqvalue;
27916 ldra_sprintf2 (&ldra_buffer[0], s,i,
zzfileid);
27917 ldra_port_write (&ldra_buffer[0]);
27925 ldra_port_write(s);
27933 ldra_sprintf2 (&ldra_buffer[0], s, i, j);
27934 ldra_port_write (&ldra_buffer[0]);
27942 ldra_sprintf3 (&ldra_buffer[0], s, i, j, k);
27943 ldra_port_write (&ldra_buffer[0]);
27951 ldra_sprintf4 (&ldra_buffer[0], s, i, j, k, l);
27952 ldra_port_write (&ldra_buffer[0]);
28071 static int branches_printed = 0;
28075 ldra_sprintf1 (&ldra_buffer[0], s, (i >> last) & ~(~0 << 8));
28076 ldra_port_write (&ldra_buffer[0]);
28077 ldra_sprintf1 (&ldra_buffer[0],
"%8d\n",
zzfileid );
28078 ldra_port_write (&ldra_buffer[0]);
28080 branches_printed += 8;
28100 #define ELEMENT(N) qqbmsoutput("%8d", bitmapstruct.element##N); 28101 #define LASTELEMENT 28102 #include "adc_63zbelem.def" TMR_PRESCALE DRV_TMR3_PrescalerGet(void)
bool PLIB_SPI_ReceiverFIFOIsEmpty(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXDisabled(DMA_MODULE_ID index)
void DRV_USART_TasksError(SYS_MODULE_OBJ object)
void * PLIB_USART_TransmitterAddressGet(USART_MODULE_ID index)
uint8_t PLIB_DMA_ChannelBitsGet(DMA_MODULE_ID index)
void PLIB_USART_TransmitterEnable(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticeEdgeStatus(PORTS_MODULE_ID index)
void SYS_DMA_Suspend(void)
bool DRV_USART_ReceiverBufferIsEmpty(const DRV_HANDLE handle)
void PLIB_PORTS_ChangeNoticeInIdlePerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
SPI_BAUD_RATE_CLOCK baudClockSource
void DRV_ADC_Initialize(void)
DRV_USART_TRANSFER_STATUS DRV_USART0_TransferStatus(void)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWrite2(DRV_HANDLE handle, void *txBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
bool PLIB_PORTS_ExistsPortsDirection(PORTS_MODULE_ID index)
uint32_t DRV_TMR4_PeriodValueGet(void)
size_t DRV_USART_BufferProcessedSizeGet(DRV_USART_BUFFER_HANDLE bufferHandle)
static void qqoutput0(FILEPOINT char *s)
bool PLIB_USART_ExistsReceiverIdleStateLowEnable(USART_MODULE_ID index)
void PLIB_DMA_CRCWriteByteOrderAlter(DMA_MODULE_ID index)
DRV_USART_ERROR DRV_USART0_ErrorGet(void)
bool PLIB_DMA_ExistsCRCBitOrder(DMA_MODULE_ID index)
static void qqoutput3(FILEPOINT char *s, int i, int j, int k)
bool PLIB_DMA_ExistsChannelXTrigger(DMA_MODULE_ID index)
bool PLIB_DMA_IsBusy(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXDestinationSize(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXEvent(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsLastBusAccess(DMA_MODULE_ID index)
void PLIB_PORTS_PinOpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
INT_SOURCE interruptSource
SYS_STATUS SYS_DEBUG_Status(SYS_MODULE_OBJ object)
bool PLIB_SPI_ExistsErrorInterruptControl(SPI_MODULE_ID index)
void(* DRV_USART_BUFFER_EVENT_HANDLER)(DRV_USART_BUFFER_EVENT event, DRV_USART_BUFFER_HANDLE bufferHandle, uintptr_t context)
bool PLIB_SPI_ExistsEnableControl(SPI_MODULE_ID index)
void SYS_DMA_ChannelDisable(SYS_DMA_CHANNEL_HANDLE handle)
void DRV_PMP0_TimingSet(PMP_DATA_WAIT_STATES dataWait, PMP_STROBE_WAIT_STATES strobeWait, PMP_DATA_HOLD_STATES dataHold)
void PLIB_SPI_BufferWrite(SPI_MODULE_ID index, uint8_t data)
void PLIB_USART_ReceiverAddressDetectEnable(USART_MODULE_ID index)
void DRV_TMR0_CounterValueSet(uint32_t value)
DRV_TMR_CLIENT_STATUS DRV_TMR3_ClientStatus(void)
void DRV_TMR4_StopInIdleEnable(void)
static void DRV_TMR0_Tasks(void)
void DRV_USART0_Deinitialize(void)
bool PLIB_SPI_ExistsFIFOShiftRegisterEmptyStatus(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsBusy(DMA_MODULE_ID index)
bool SYS_PORTS_PinRead(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_SPI_ExistsTransmitUnderRunStatus(SPI_MODULE_ID index)
void PLIB_USART_WakeOnStartDisable(USART_MODULE_ID index)
bool PLIB_USART_ExistsLoopback(USART_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR4_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void PLIB_DMA_ChannelXPeripheralAddressSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t peripheraladdress)
TMR_PRESCALE DRV_TMR2_PrescalerGet(void)
void PLIB_DMA_ChannelXReloadEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsFrameSyncPulseWidth(SPI_MODULE_ID index)
void PLIB_SPI_PinEnable(SPI_MODULE_ID index, SPI_PIN pin)
void DRV_TMR_Stop(DRV_HANDLE handle)
void DRV_TMR_CounterClear(DRV_HANDLE handle)
void PLIB_USART_RunInOverflowEnable(USART_MODULE_ID index)
void PLIB_SPI_ErrorInterruptDisable(SPI_MODULE_ID index, SPI_ERROR_INTERRUPT error)
void PLIB_PORTS_ChangeNoticePullDownPerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
SPI_FRAME_PULSE_POLARITY framePulsePolarity
void SYS_DMA_ChannelTransferAdd(SYS_DMA_CHANNEL_HANDLE handle, const void *srcAddr, size_t srcSize, const void *destAddr, size_t destSize, size_t cellSize)
bool PLIB_DMA_ExistsChannelXPatternIgnore(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsFIFOInterruptMode(SPI_MODULE_ID index)
void DRV_USART0_Close(void)
void DRV_TMR4_PeriodValueSet(uint32_t value)
void PLIB_USART_ReceiverIdleStateLowDisable(USART_MODULE_ID index)
DRV_USART_BAUD_SET_RESULT DRV_USART0_BaudSet(uint32_t baud)
void SYS_DEBUG_Deinitialize(SYS_MODULE_OBJ object)
void PLIB_SPI_FrameSyncPulseEdgeSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_EDGE edge)
DRV_USART_OPERATION_MODE_DATA modeData
uint32_t SYS_DMA_ChannelCRCGet(void)
void PLIB_USART_WakeOnStartEnable(USART_MODULE_ID index)
DRV_TMR_CLIENT_STATUS DRV_TMR4_ClientStatus(void)
bool PLIB_SPI_ReadDataIsSignExtended(SPI_MODULE_ID index)
void PLIB_SPI_ClockPolaritySelect(SPI_MODULE_ID index, SPI_CLOCK_POLARITY polarity)
bool DRV_IC_BufferIsEmpty(DRV_HANDLE handle)
uint16_t PLIB_DMA_ChannelXSourcePointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
DMA_PING_PONG_MODE PLIB_DMA_ChannelXPingPongModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void DRV_TMR1_DeInitialize(void)
void DRV_USART_Deinitialize(SYS_MODULE_OBJ object)
void PLIB_USART_RunInSleepModeDisable(USART_MODULE_ID index)
void DRV_TMR0_PeriodValueSet(uint32_t value)
DRV_HANDLE DRV_IC_Start(const SYS_MODULE_INDEX drvIndex, const DRV_IO_INTENT intent)
void PLIB_SPI_SlaveEnable(SPI_MODULE_ID index)
void PLIB_USART_IrDAEnable(USART_MODULE_ID index)
void PLIB_DMA_SuspendDisable(DMA_MODULE_ID index)
static int qqqstructzzopen
bool PLIB_USART_ExistsIrDA(USART_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXPatternDataGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void SYS_DMA_Tasks(SYS_MODULE_OBJ object, DMA_CHANNEL activeChannel)
void PLIB_USART_BaudRateSet(USART_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
DRV_USART_LINE_CONTROL_SET_RESULT
void PLIB_PORTS_CnPinsPullUpEnable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
void PLIB_PORTS_AnPinsModeSelect(PORTS_MODULE_ID index, PORTS_AN_PIN anPins, PORTS_PIN_MODE mode)
DMA_CRC_BYTE_ORDER PLIB_DMA_CRCByteOrderGet(DMA_MODULE_ID index)
int32_t DRV_SPI_ClientConfigure(DRV_HANDLE handle, const DRV_SPI_CLIENT_DATA *cfgData)
void SYS_DMA_ChannelSuspend(SYS_DMA_CHANNEL_HANDLE handle)
uint8_t DRV_USART0_ReadByte(void)
static struct bitmapstruct_t bitmapstruct
PORTS_DATA_TYPE SYS_PORTS_InterruptStatusGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
static ADC_STATES A_STATES
static void DRV_TMR1_Open(void)
void PLIB_DMA_ChannelXPrioritySelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_PRIORITY channelPriority)
bool PLIB_DMA_ExistsChannelXChainEnbl(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePerPortTurnOn(PORTS_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddRead(DRV_HANDLE handle, void *rxBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
void PLIB_DMA_CRCAppendModeDisable(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXTriggerEnable(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
uint32_t DRV_TMR3_PeriodValueGet(void)
void PLIB_PORTS_ChangeNoticePullUpEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
bool PLIB_USART_WakeOnStartIsEnabled(USART_MODULE_ID index)
void PLIB_PORTS_DirectionInputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_PORTS_PinOpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ExistsStartTransfer(DMA_MODULE_ID index)
DRV_TMR_CLIENT_STATUS DRV_TMR_ClientStatus(DRV_HANDLE handle)
void PLIB_USART_ReceiverEnable(USART_MODULE_ID index)
struct _DRV_SPI_INIT DRV_SPI_INIT
uint8_t PLIB_SPI_BufferRead(SPI_MODULE_ID index)
void(* DRV_SPI_BUFFER_EVENT_HANDLER)(DRV_SPI_BUFFER_EVENT event, DRV_SPI_BUFFER_HANDLE bufferHandle, void *context)
DRV_USART_BAUD_SET_RESULT
void PLIB_USART_StopInIdleEnable(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsPinModePerPort(PORTS_MODULE_ID index)
void PLIB_DMA_SuspendEnable(DMA_MODULE_ID index)
static void DRV_TMR1_Tasks(void)
void SYS_PORTS_ChangeNotificationGlobalEnable(PORTS_MODULE_ID index)
int16_t PLIB_USART_Receiver9BitsReceive(USART_MODULE_ID index)
bool PLIB_DMA_ExistsStopInIdle(DMA_MODULE_ID index)
void PLIB_SPI_AudioProtocolDisable(SPI_MODULE_ID index)
void DRV_TMR4_StopInIdleDisable(void)
DRV_TMR_CLIENT_STATUS DRV_TMR0_ClientStatus(void)
INT_SOURCE dmaInterruptReceive
SYS_MODULE_INIT moduleInit
bool PLIB_SPI_FrameErrorStatusGet(SPI_MODULE_ID index)
struct _DRV_SPI_CLIENT_DATA DRV_SPI_CLIENT_DATA
PORTS_DATA_TYPE SYS_PORTS_Read(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
static void DRV_TMR0_Close(void)
bool PLIB_SPI_ExistsFIFOCount(SPI_MODULE_ID index)
void DRV_USART_BufferEventHandlerSet(const DRV_HANDLE handle, const DRV_USART_BUFFER_EVENT_HANDLER eventHandler, const uintptr_t context)
size_t SYS_DMA_ChannelDestinationTransferredSizeGet(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_SPI_ExistsStopInIdleControl(SPI_MODULE_ID index)
uint8_t jobQueueReserveSize
bool PLIB_SPI_ExistsTransmitBufferEmptyStatus(SPI_MODULE_ID index)
static void DRV_TMR2_DeInitialize(void)
bool PLIB_SPI_ExistsClockPolarity(SPI_MODULE_ID index)
void PLIB_DMA_Disable(DMA_MODULE_ID index)
void SYS_PORTS_RemapInput(PORTS_MODULE_ID index, PORTS_REMAP_INPUT_FUNCTION function, PORTS_REMAP_INPUT_PIN remapPin)
TMR_PRESCALE DRV_TMR4_PrescalerGet(void)
USART_ERROR PLIB_USART_ErrorsGet(USART_MODULE_ID index)
void PLIB_DMA_ChannelXEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
SYS_MODULE_INIT moduleInit
bool PLIB_DMA_IsEnabled(DMA_MODULE_ID index)
DRV_USART_CLIENT_STATUS DRV_USART0_ClientStatus(void)
void DRV_TMR_AlarmEnable(DRV_HANDLE handle, bool enable)
uint32_t PLIB_DMA_ChannelXDestinationStartAddressGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void SYS_PORTS_PinOpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_PORTS_PinModeSelect(PORTS_MODULE_ID index, PORTS_ANALOG_PIN pin, PORTS_PIN_MODE mode)
SYS_DMA_CHANNEL_HANDLE SYS_DMA_ChannelAllocate(DMA_CHANNEL channel)
bool PLIB_PORTS_ExistsChangeNoticePerPortInIdle(PORTS_MODULE_ID index)
void DRV_USART_Close(const DRV_HANDLE handle)
uint32_t DRV_TMR3_CounterFrequencyGet(void)
void PLIB_SPI_FIFOInterruptModeSelect(SPI_MODULE_ID index, SPI_FIFO_INTERRUPT mode)
bool PLIB_SPI_ExistsAudioProtocolControl(SPI_MODULE_ID index)
static DRV_TMR_OPERATION_MODE DRV_TMR4_OperationModeGet(void)
INT_SOURCE interruptTransmit
void PLIB_DMA_ChannelXAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_ADDRESSING_MODE channelAddressMode)
void PLIB_DMA_ChannelXChainEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsInputSamplePhase(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsFrameSyncPulsePolarity(SPI_MODULE_ID index)
bool PLIB_USART_ModuleIsBusy(USART_MODULE_ID index)
static int qqqisinitialised
void SYS_PORTS_PinPullUpEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DMA_TRANSFER_MODE PLIB_DMA_ChannelXOperatingTransferModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_USART_ByteReceiveCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
void PLIB_DMA_CRCDataWrite(DMA_MODULE_ID index, uint32_t DMACRCdata)
void DRV_ADC_DeInitialize(void)
void PLIB_DMA_ChannelXINTSourceFlagClear(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
bool DRV_ADC_SamplesAvailable(uint8_t bufIndex)
DMA_CRC_TYPE PLIB_DMA_CRCTypeGet(DMA_MODULE_ID index)
SYS_MODULE_OBJ DRV_TMR_Initialize(const SYS_MODULE_INDEX drvIndex, const SYS_MODULE_INIT *const init)
uint16_t PLIB_DMA_ChannelXDestinationPointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_SPI_ExistsAudioProtocolMode(SPI_MODULE_ID index)
void DRV_USART0_WriteByte(const uint8_t byte)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWriteRead(DRV_HANDLE handle, void *txBuffer, size_t txSize, void *rxBuffer, size_t rxSize, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
void PLIB_PORTS_ChangeNoticeInIdleDisable(PORTS_MODULE_ID index)
bool PLIB_SPI_TransmitBufferIsEmpty(SPI_MODULE_ID index)
bool DRV_TMR_AlarmRegister(DRV_HANDLE handle, uint32_t divider, bool isPeriodic, uintptr_t context, DRV_TMR_CALLBACK callBack)
PORTS_CHANGE_NOTICE_METHOD PLIB_PORTS_ChannelChangeNoticeMethodGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_SPI_FrameErrorStatusClear(SPI_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticeEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_USART_BaudRateHighDisable(USART_MODULE_ID index)
void PLIB_DMA_CRCXOREnableSet(DMA_MODULE_ID index, uint32_t DMACRCXOREnableMask)
void DRV_TMR2_Initialize(void)
uint32_t DRV_TMR1_CounterValueGet(void)
INT_SOURCE txInterruptSource
bool PLIB_USART_ReceiverFramingErrorHasOccurred(USART_MODULE_ID index)
DMA_CHANNEL_PRIORITY PLIB_DMA_ChannelXPriorityGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_ExistsChangeNoticePullUp(PORTS_MODULE_ID index)
void PLIB_USART_ReceiverAddressAutoDetectDisable(USART_MODULE_ID index)
DMA_SOURCE_ADDRESSING_MODE PLIB_DMA_ChannelXSourceAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_TMR0_CounterClear(void)
unsigned int DRV_USART0_TransmitBufferSizeGet(void)
bool PLIB_DMA_ExistsCRCData(DMA_MODULE_ID index)
bool PLIB_PORTS_PinGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_USART_ReceiverAddressIsReceived(USART_MODULE_ID index)
void PLIB_SPI_FrameSyncPulseCounterSelect(SPI_MODULE_ID index, SPI_FRAME_SYNC_PULSE pulse)
void PLIB_PORTS_ChannelModeSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK modeMask, PORTS_PIN_MODE mode)
void SYS_DEBUG_Tasks(SYS_MODULE_OBJ object)
void PLIB_DMA_CRCDisable(DMA_MODULE_ID index)
static void qqoutput2(FILEPOINT char *s, int i, int j)
void PLIB_PORTS_ChannelChangeNoticePullDownDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
USART_BRG_CLOCK_SOURCE PLIB_USART_BRGClockSourceGet(USART_MODULE_ID index)
DRV_USART_TRANSFER_STATUS
void PLIB_USART_TransmitterBreakSend(USART_MODULE_ID index)
void SYS_PORTS_Set(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value, PORTS_DATA_MASK mask)
bool PLIB_DMA_ExistsCRCByteOrder(DMA_MODULE_ID index)
void PLIB_USART_ReceiverAddressAutoDetectEnable(USART_MODULE_ID index, int8_t Mask)
SYS_DMA_CHANNEL_IGNORE_MATCH
SPI_FRAME_PULSE_DIRECTION framePulseDirection
void PLIB_DMA_ChannelXChainDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_SPI_CommunicationWidthSelect(SPI_MODULE_ID index, SPI_COMMUNICATION_WIDTH width)
uint32_t DRV_TMR4_CounterFrequencyGet(void)
void DRV_TMR1_StopInIdleDisable(void)
PORTS_PIN_SLEW_RATE PLIB_PORTS_PinSlewRateGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uint16_t PLIB_SPI_BufferRead16bit(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXDataSizeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_DATA_SIZE channelDataSize)
static int adc_63zscanf(char *qqscan_str)
void PLIB_DMA_StartTransferSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_TMR4_CounterClear(void)
uint32_t DRV_TMR4_CounterValueGet(void)
bool PLIB_DMA_ExistsChannelXCellSize(DMA_MODULE_ID index)
void PLIB_SPI_FIFODisable(SPI_MODULE_ID index)
SYS_MODULE_OBJ spiObjectIdx1
uint32_t PLIB_DMA_CRCDataRead(DMA_MODULE_ID index)
SYS_ERROR_LEVEL gblErrLvl
void PLIB_PORTS_ChannelChangeNoticeMethodSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_CHANGE_NOTICE_METHOD changeNoticeMethod)
static void qqqqinitialise(int ii)
bool PLIB_USART_ExistsBaudRate(USART_MODULE_ID index)
void(* ldra_void_function)()
void PLIB_DMA_StopInIdleEnable(DMA_MODULE_ID index)
bool DRV_SPIn_ReceiverBufferIsFull(void)
DRV_SPI_PROTOCOL_TYPE spiProtocolType
void PLIB_PORTS_RemapInput(PORTS_MODULE_ID index, PORTS_REMAP_INPUT_FUNCTION inputFunction, PORTS_REMAP_INPUT_PIN remapInputPin)
void PLIB_USART_TransmitterIdleIsLowDisable(USART_MODULE_ID index)
void PLIB_PORTS_Clear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK clearMask)
void PLIB_SPI_ReceiverOverflowClear(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsFrameSyncPulseDirection(SPI_MODULE_ID index)
bool DRV_TMR3_Start(void)
void PLIB_PORTS_ChannelChangeNoticeEdgeEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK edgeRisingMask, PORTS_DATA_MASK edgeFallingMask)
SPI_FRAME_PULSE_WIDTH framePulseWidth
bool PLIB_USART_ExistsReceiver9Bits(USART_MODULE_ID index)
void PLIB_DMA_ChannelXChainToHigher(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint8_t DRV_USART_ReadByte(const DRV_HANDLE handle)
DRV_USART_CLIENT_STATUS DRV_USART_ClientStatus(DRV_HANDLE handle)
PORTS_DATA_MASK SYS_PORTS_DirectionGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
uint8_t PLIB_USART_AddressMaskGet(USART_MODULE_ID index)
void DRV_TMR1_CounterClear(void)
bool PLIB_USART_ExistsReceiver(USART_MODULE_ID index)
void PLIB_USART_BaudRateAutoDetectEnable(USART_MODULE_ID index)
void DRV_PMP0_ModeConfig(void)
void PLIB_SPI_AudioCommunicationWidthSelect(SPI_MODULE_ID index, SPI_AUDIO_COMMUNICATION_WIDTH mode)
bool PLIB_SPI_ExistsAudioTransmitMode(SPI_MODULE_ID index)
void(* DRV_USART_BYTE_EVENT_HANDLER)(const SYS_MODULE_INDEX index)
void PLIB_PORTS_PinWrite(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, bool value)
void SYS_PORTS_ChangeNotificationPullUpDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void SYS_PORTS_Write(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value)
bool PLIB_USART_ReceiverParityErrorHasOccurred(USART_MODULE_ID index)
DMA_PATTERN_LENGTH PLIB_DMA_ChannelXPatternLengthGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool DRV_TMR_GateModeClear(DRV_HANDLE handle)
void SYS_PORTS_ChangeNotificationInIdleModeDisable(PORTS_MODULE_ID index)
void PLIB_DMA_ChannelXCellSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t CellSize)
void PLIB_USART_Disable(USART_MODULE_ID index)
static void DRV_TMR3_Close(void)
DRV_TMR_CLK_SOURCES clockSource
bool PLIB_SPI_ExistsReceiverOverflow(SPI_MODULE_ID index)
void PLIB_SPI_TransmitUnderRunStatusClear(SPI_MODULE_ID index)
void DRV_TMR_AlarmPeriodSet(DRV_HANDLE handle, uint32_t value)
bool PLIB_DMA_ChannelXTriggerIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
static void DRV_TMR2_Close(void)
DMA_CHANNEL_ADDRESSING_MODE PLIB_DMA_ChannelXAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_TMR1_CounterValueSet(uint32_t value)
void PLIB_DMA_ChannelXTriggerDisable(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
void PLIB_PORTS_PinClear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_PORTS_PinChangeNoticePerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_SPI_PinDisable(SPI_MODULE_ID index, SPI_PIN pin)
bool DRV_USART0_ReceiverBufferIsEmpty(void)
uint32_t DRV_TMR_CounterFrequencyGet(DRV_HANDLE handle)
bool PLIB_USART_ExistsReceiverEnable(USART_MODULE_ID index)
void DRV_TMR_AlarmDeregister(DRV_HANDLE handle)
void PLIB_DMA_CRCPolynomialLengthSet(DMA_MODULE_ID index, uint8_t polyLength)
void PLIB_USART_RunInOverflowDisable(USART_MODULE_ID index)
bool PLIB_SPI_Exists16bitBuffer(SPI_MODULE_ID index)
void DRV_TMR2_StopInIdleDisable(void)
void SYS_PORTS_Initialize()
bool PLIB_SPI_Exists32bitBuffer(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsSlewRateControl(PORTS_MODULE_ID index)
bool PLIB_PORTS_ExistsRemapOutput(PORTS_MODULE_ID index)
void PLIB_DMA_CRCByteOrderSelect(DMA_MODULE_ID index, DMA_CRC_BYTE_ORDER byteOrder)
void PLIB_SPI_SlaveSelectDisable(SPI_MODULE_ID index)
void PLIB_PORTS_CnPinsDisable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
bool PLIB_SPI_IsBusy(SPI_MODULE_ID index)
void PLIB_USART_RunInSleepModeEnable(USART_MODULE_ID index)
bool PLIB_SPI_ReceiverHasOverflowed(SPI_MODULE_ID index)
bool DRV_TMR0_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
uint32_t DRV_TMR2_CounterValueGet(void)
void SYS_PORTS_ChangeNotificationEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum, SYS_PORTS_PULLUP_PULLDOWN_STATUS value)
uint8_t PLIB_SPI_FIFOCountGet(SPI_MODULE_ID index, SPI_FIFO_TYPE type)
static SYS_STATUS DRV_TMR2_Status(void)
bool PLIB_DMA_ChannelXPatternIgnoreByteIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsBaudRate(SPI_MODULE_ID index)
void PLIB_SPI_FIFOEnable(SPI_MODULE_ID index)
void DRV_USART_TasksReceive(SYS_MODULE_OBJ object)
bool DRV_USART0_TransmitBufferIsFull(void)
void DRV_USART0_TasksReceive(void)
bool PLIB_PORTS_ExistsLatchRead(PORTS_MODULE_ID index)
void PLIB_DMA_ChannelXSourceAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_SOURCE_ADDRESSING_MODE sourceAddressMode)
void PLIB_PORTS_ChangeNoticeInIdleEnable(PORTS_MODULE_ID index)
DRV_SPI_BUFFER_TYPE bufferType
void DRV_USART0_TasksError(void)
void DRV_TMR_Close(DRV_HANDLE handle)
void PLIB_PORTS_Toggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK toggleMask)
void DRV_IC0_Initialize(void)
void PLIB_USART_HandshakeModeSelect(USART_MODULE_ID index, USART_HANDSHAKE_MODE handshakeConfig)
bool PLIB_PORTS_ExistsChangeNoticeInIdle(PORTS_MODULE_ID index)
void PLIB_USART_IrDADisable(USART_MODULE_ID index)
SYS_DMA_CRC_WRITE_ORDER writeOrder
void DRV_TMR0_StopInIdleEnable(void)
void PLIB_PORTS_ChannelChangeNoticeDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
SYS_STATUS DRV_TMR_Status(SYS_MODULE_OBJ object)
void PLIB_DMA_ChannelXDisabledDisablesEvents(DMA_MODULE_ID index, DMA_CHANNEL channel)
PORTS_DATA_MASK PLIB_PORTS_DirectionGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_SPI_FramedCommunicationDisable(SPI_MODULE_ID index)
bool PLIB_DMA_ChannelXAutoIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ChannelXReloadIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_SPI_Deinitialize(SYS_MODULE_OBJ object)
DRV_SPI_BUFFER_EVENT DRV_SPI_BufferStatus(DRV_SPI_BUFFER_HANDLE bufferHandle)
void PLIB_PORTS_ChangeNoticePullUpDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
static SYS_STATUS DRV_TMR4_Status(void)
static int adc_63zqendz(int qqqi)
void PLIB_USART_LoopbackEnable(USART_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePullUpPerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_ChannelPrioritySelect(DMA_MODULE_ID index, DMA_CHANNEL_PRIORITY channelPriority)
bool PLIB_USART_ExistsEnable(USART_MODULE_ID index)
static void DRV_TMR3_Open(void)
void PLIB_PORTS_PinSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_USART_ExistsBaudRateAutoDetect(USART_MODULE_ID index)
uint16_t DRV_IC_Capture16BitDataRead(DRV_HANDLE handle)
void PLIB_PORTS_ChannelChangeNoticePullUpDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void DRV_ADC0_Close(void)
void SYS_DMA_Resume(void)
void DRV_ADC1_Close(void)
uint32_t DRV_TMR1_PeriodValueGet(void)
bool PLIB_USART_ExistsTransmitterBreak(USART_MODULE_ID index)
bool DRV_TMR2_Start(void)
void DRV_IC_Stop(DRV_HANDLE handle)
void PLIB_USART_BaudSetAndEnable(USART_MODULE_ID index, uint32_t systemClock, uint32_t baud)
bool PLIB_DMA_ExistsChannelXDestinationPointer(DMA_MODULE_ID index)
DMA_CHANNEL_DATA_SIZE PLIB_DMA_ChannelXDataSizeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ChannelXNullWriteModeIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
DRV_SPI_BUFFER_EVENT_HANDLER operationStarting
bool PLIB_PORTS_ExistsPortsOpenDrain(PORTS_MODULE_ID index)
bool PLIB_SPI_ExistsReceiveBufferStatus(SPI_MODULE_ID index)
void PLIB_PORTS_PinModePerPortSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_PIN_MODE mode)
INT_SOURCE dmaInterruptTransmit
void SYS_PORTS_PinPullUpDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_USART_AddressMaskSet(USART_MODULE_ID index, uint8_t mask)
void PLIB_DMA_CRCEnable(DMA_MODULE_ID index)
unsigned int queueSizeReceive
void SYS_DMA_ChannelForceStart(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_DMA_SuspendIsEnabled(DMA_MODULE_ID index)
bool PLIB_USART_ExistsTransmitterBufferFullStatus(USART_MODULE_ID index)
bool PLIB_SPI_ReceiverBufferIsFull(SPI_MODULE_ID index)
bool PLIB_USART_ExistsTransmitterEmptyStatus(USART_MODULE_ID index)
bool PLIB_SPI_ExistsFIFOControl(SPI_MODULE_ID index)
void SYS_PORTS_PinPullDownEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
size_t DRV_USART_BufferCompletedBytesGet(DRV_USART_BUFFER_HANDLE bufferHandle)
DRV_USART_HANDSHAKE handshake
void PLIB_USART_ReceiverAddressDetectDisable(USART_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR_DividerRangeGet(DRV_HANDLE handle, DRV_TMR_DIVIDER_RANGE *pDivRange)
void(* SYS_DMA_CHANNEL_TRANSFER_EVENT_HANDLER)(SYS_DMA_TRANSFER_EVENT event, SYS_DMA_CHANNEL_HANDLE handle, uintptr_t contextHandle)
unsigned int DRV_USART_ReceiverBufferSizeGet(const DRV_HANDLE handle)
void PLIB_PORTS_ChangeNoticeInIdlePerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void DRV_TMR4_Initialize(void)
void(* DRV_TMR_CALLBACK)(uintptr_t context, uint32_t alarmCount)
void PLIB_USART_LoopbackDisable(USART_MODULE_ID index)
bool DRV_IC0_BufferIsEmpty(void)
bool PLIB_USART_ExistsReceiverAddressDetect(USART_MODULE_ID index)
static void DRV_TMR0_DeInitialize(void)
void PLIB_DMA_ChannelXDisabledEnablesEvents(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_SPI_AudioProtocolModeSelect(SPI_MODULE_ID index, SPI_AUDIO_PROTOCOL mode)
SYS_DMA_ERROR SYS_DMA_ChannelErrorGet(SYS_DMA_CHANNEL_HANDLE handle)
void qqqtotalupload(void)
void PLIB_SPI_BufferClear(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsSlaveSelectControl(SPI_MODULE_ID index)
uint32_t PLIB_DMA_CRCXOREnableGet(DMA_MODULE_ID index)
void DRV_TMR_CounterValueSet(DRV_HANDLE handle, uint32_t counterPeriod)
uint8_t PLIB_USART_AddressGet(USART_MODULE_ID index)
void PLIB_USART_OperationModeSelect(USART_MODULE_ID index, USART_OPERATION_MODE operationmode)
SPI_FRAME_PULSE_EDGE framePulseEdge
bool PLIB_USART_ExistsReceiverInterruptMode(USART_MODULE_ID index)
bool PLIB_DMA_ChannelXBufferedDataIsWritten(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_ChangeNoticeEnable(PORTS_MODULE_ID index)
bool PLIB_USART_ExistsTransmitter9BitsSend(USART_MODULE_ID index)
void DRV_TMR_Tasks(SYS_MODULE_OBJ object)
void SYS_DMA_ChannelSetupMatchAbortMode(SYS_DMA_CHANNEL_HANDLE handle, uint16_t pattern, DMA_PATTERN_LENGTH length, SYS_DMA_CHANNEL_IGNORE_MATCH ignore, uint8_t ignorePattern)
static void DRV_TMR3_Tasks(void)
bool DRV_TMR1_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
bool PLIB_DMA_ExistsCRCWriteByteOrder(DMA_MODULE_ID index)
void PLIB_USART_TransmitterByteSend(USART_MODULE_ID index, int8_t data)
void DRV_TMR2_CounterValueSet(uint32_t value)
void PLIB_SPI_MasterEnable(SPI_MODULE_ID index)
DRV_HANDLE DRV_SPI_Open(const SYS_MODULE_INDEX drvIndex, const DRV_IO_INTENT ioIntent)
DRV_USART_INIT_FLAGS flags
void PLIB_USART_BRGClockSourceSelect(USART_MODULE_ID index, USART_BRG_CLOCK_SOURCE brgClockSource)
void DRV_TMR3_Initialize(void)
void PLIB_PORTS_PinDirectionInputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_PORTS_ChannelChangeNoticePullDownEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
#define DRV_IC_Open(drvIndex, intent)
void PLIB_SPI_ErrorInterruptEnable(SPI_MODULE_ID index, SPI_ERROR_INTERRUPT error)
uint8_t PLIB_DMA_CRCPolynomialLengthGet(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsBusStatus(SPI_MODULE_ID index)
void PLIB_PORTS_OpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
unsigned int queueSizeTransmit
uint32_t DRV_TMR2_CounterFrequencyGet(void)
void SYS_DMA_ChannelTransferEventHandlerSet(SYS_DMA_CHANNEL_HANDLE handle, const SYS_DMA_CHANNEL_TRANSFER_EVENT_HANDLER eventHandler, const uintptr_t contextHandle)
bool PLIB_USART_RunInSleepModeIsEnabled(USART_MODULE_ID index)
void DRV_PMP0_Write(uint8_t data)
void DRV_PMP0_Initialize(void)
uint16_t PLIB_DMA_ChannelXStartAddressOffsetGet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_ADDRESS_OFFSET_TYPE offset)
uintptr_t DRV_USART_BUFFER_HANDLE
void PLIB_PORTS_DirectionOutputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
DMA_CRC_BIT_ORDER bitOrder
bool PLIB_DMA_LastBusAccessIsWrite(DMA_MODULE_ID index)
bool DRV_TMR_GateModeSet(DRV_HANDLE handle)
bool PLIB_DMA_ExistsCRC(DMA_MODULE_ID index)
void PLIB_USART_StopInIdleDisable(USART_MODULE_ID index)
bool PLIB_SPI_ExistsMasterControl(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsReadDataSignStatus(SPI_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePerPortTurnOn(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_SPI_BaudRateSet(SPI_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
bool PLIB_USART_ExistsWakeOnStart(USART_MODULE_ID index)
bool PLIB_SPI_TransmitBufferIsFull(SPI_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXDestinationSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_DMA_ExistsCRCXOREnable(DMA_MODULE_ID index)
DRV_USART_LINE_CONTROL_SET_RESULT DRV_USART0_LineControlSet(DRV_USART_LINE_CONTROL lineControlMode)
static void qqoutput4(FILEPOINT char *s, int i, int j, int k, int l)
bool PLIB_DMA_ExistsChannelXPatternData(DMA_MODULE_ID index)
void SYS_DMA_ChannelForceAbort(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_SPI_ExistsCommunicationWidth(SPI_MODULE_ID index)
void DRV_TMR3_StopInIdleEnable(void)
DRV_SPI_BUFFER_EVENT_HANDLER operationEnded
bool PLIB_DMA_ExistsAbortTransfer(DMA_MODULE_ID index)
static DRV_TMR_OPERATION_MODE DRV_TMR2_OperationModeGet(void)
void PLIB_PORTS_PinChangeNoticeDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_DMA_ChannelXAutoEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
CLK_BUSES_PERIPHERAL spiClk
bool PLIB_PORTS_ExistsChangeNotice(PORTS_MODULE_ID index)
bool PLIB_DMA_ExistsChannelX(DMA_MODULE_ID index)
void PLIB_SPI_StopInIdleDisable(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsBuffer(SPI_MODULE_ID index)
DRV_TMR_CLIENT_STATUS DRV_TMR2_ClientStatus(void)
bool PLIB_USART_ExistsReceiverOverrunStatus(USART_MODULE_ID index)
void PLIB_SPI_FrameSyncPulseDirectionSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_DIRECTION direction)
bool PLIB_DMA_ExistsCRCAppendMode(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXPatternDataSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t patternData)
SYS_MODULE_OBJ spiObjectIdx0
void PLIB_DMA_ChannelXINTSourceFlagSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void PLIB_SPI_Disable(SPI_MODULE_ID index)
DRV_USART_LINE_CONTROL lineControl
bool PLIB_USART_ExistsReceiverParityErrorStatus(USART_MODULE_ID index)
void PLIB_PORTS_ChangeNoticeDisable(PORTS_MODULE_ID index)
bool PLIB_PORTS_ExistsChannelChangeNoticeMethod(PORTS_MODULE_ID index)
PORTS_DATA_TYPE SYS_PORTS_LatchedGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void DRV_TMR3_StopInIdleDisable(void)
uint8_t PLIB_DMA_ChannelXPatternIgnoreGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXAbortIRQSet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRIGGER_SOURCE IRQ)
DMA_DESTINATION_ADDRESSING_MODE PLIB_DMA_ChannelXDestinationAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_Set(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value, PORTS_DATA_MASK mask)
bool PLIB_DMA_CRCIsEnabled(DMA_MODULE_ID index)
SPI_COMMUNICATION_WIDTH commWidth
static SYS_STATUS DRV_TMR0_Status(void)
void PLIB_DMA_StopInIdleDisable(DMA_MODULE_ID index)
bool PLIB_PORTS_PinChangeNoticeEdgeHasOccurred(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool SYS_DMA_ChannelIsBusy(SYS_DMA_CHANNEL_HANDLE handle)
static SYS_STATUS DRV_TMR1_Status(void)
bool PLIB_USART_TransmitterIsEmpty(USART_MODULE_ID index)
bool PLIB_DMA_ExistsRecentAddress(DMA_MODULE_ID index)
void PLIB_PORTS_PinToggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_SPI_InputSamplePhaseSelect(SPI_MODULE_ID index, SPI_INPUT_SAMPLING_PHASE phase)
int8_t PLIB_USART_ReceiverByteReceive(USART_MODULE_ID index)
void PLIB_DMA_BusyActiveSet(DMA_MODULE_ID index)
bool PLIB_DMA_ChannelXCollisionStatus(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_COLLISION collisonType)
void SYS_DMA_ChannelAbortEventSet(SYS_DMA_CHANNEL_HANDLE handle, DMA_TRIGGER_SOURCE eventSrc)
bool PLIB_USART_ExistsBaudRateHigh(USART_MODULE_ID index)
void SYS_PORTS_OpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_PORTS_PinDirectionOutputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_PORTS_PinGetLatched(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWriteRead2(DRV_HANDLE handle, void *txBuffer, size_t txSize, void *rxBuffer, size_t rxSize, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
void DRV_TMR3_PeriodValueSet(uint32_t value)
void PLIB_DMA_ChannelXDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
size_t SYS_DMA_ChannelSourceTransferredSizeGet(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_SPI_ExistsTransmitBufferFullStatus(SPI_MODULE_ID index)
bool PLIB_USART_ExistsReceiverFramingErrorStatus(USART_MODULE_ID index)
bool DRV_TMR_AlarmDisable(DRV_HANDLE handle)
void PLIB_DMA_AbortTransferSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
DRV_TMR_OPERATION_MODE DRV_TMR1_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void DRV_TMR2_StopInIdleEnable(void)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWrite(DRV_HANDLE handle, void *txBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
bool PLIB_DMA_ExistsChannelXCellProgressPointer(DMA_MODULE_ID index)
SYS_STATUS DRV_USART_Status(SYS_MODULE_OBJ object)
void PLIB_USART_TransmitterDisable(USART_MODULE_ID index)
SYS_DMA_CHANNEL_CRC_MODE mode
DRV_USART_ERROR DRV_USART_ErrorGet(const DRV_HANDLE client)
static SYS_STATUS DRV_TMR3_Status(void)
bool PLIB_USART_ExistsStopInIdle(USART_MODULE_ID index)
void PLIB_SPI_AudioErrorEnable(SPI_MODULE_ID index, SPI_AUDIO_ERROR error)
unsigned int DRV_USART_TransmitBufferSizeGet(const DRV_HANDLE handle)
static DRV_TMR_OPERATION_MODE DRV_TMR0_OperationModeGet(void)
TMR_PRESCALE DRV_TMR_PrescalerGet(DRV_HANDLE handle)
bool PLIB_SPI_ExistsAudioCommunicationWidth(SPI_MODULE_ID index)
DRV_USART_BUFFER_RESULT DRV_USART_BufferRemove(DRV_USART_BUFFER_HANDLE bufferHandle)
SYS_PORTS_PULLUP_PULLDOWN_STATUS
INT_SOURCE interruptReceive
size_t DRV_USART_Read(const DRV_HANDLE handle, void *buffer, const size_t numbytes)
bool PLIB_DMA_ChannelXEventIsDetected(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint32_t PLIB_SPI_BufferRead32bit(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsCRCType(DMA_MODULE_ID index)
static void DRV_TMR2_Tasks(void)
void PLIB_USART_ReceiverInterruptModeSelect(USART_MODULE_ID index, USART_RECEIVE_INTR_MODE interruptMode)
bool PLIB_USART_ExistsReceiverIdleStatus(USART_MODULE_ID index)
uint32_t PLIB_DMA_RecentAddressAccessed(DMA_MODULE_ID index)
void PLIB_PORTS_ChannelSlewRateSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK channelMask, PORTS_PIN_SLEW_RATE slewRate)
SYS_ERROR_LEVEL errorLevel
bool PLIB_PORTS_ExistsChangeNoticePerPortStatus(PORTS_MODULE_ID index)
void DRV_TMR2_PeriodValueSet(uint32_t value)
void PLIB_DMA_ChannelXNullWriteModeEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
SYS_MODULE_OBJ DRV_USART_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
DRV_SPI_BUFFER_EVENT_HANDLER operationEnded
bool PLIB_SPI_ExistsAudioErrorControl(SPI_MODULE_ID index)
bool DRV_TMR0_Start(void)
static void DRV_TMR4_Close(void)
static void DRV_TMR0_Open(void)
void PLIB_PORTS_ChangeNoticePerPortTurnOff(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
DMA_CHANNEL dmaChannelReceive
bool DRV_TMR4_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
bool PLIB_DMA_ExistsCRCPolynomialLength(DMA_MODULE_ID index)
void PLIB_DMA_Enable(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXPatternIgnoreSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint8_t pattern)
bool PLIB_USART_ExistsTransmitterIdleIsLow(USART_MODULE_ID index)
bool DRV_TMR_ClockSet(DRV_HANDLE handle, DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE preScale)
void PLIB_USART_BaudRateHighEnable(USART_MODULE_ID index)
void PLIB_DMA_CRCTypeSet(DMA_MODULE_ID index, DMA_CRC_TYPE CRCType)
void PLIB_PORTS_ChannelChangeNoticeEdgeDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK edgeRisingMask, PORTS_DATA_MASK edgeFallingMask)
void PLIB_PORTS_OpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_SPI_ExistsFrameErrorStatus(SPI_MODULE_ID index)
DRV_TMR_OPERATION_MODE mode
bool PLIB_USART_ExistsReceiverDataAvailableStatus(USART_MODULE_ID index)
void PLIB_PORTS_PinModeSelect(PORTS_MODULE_ID index, PORTS_ANALOG_PIN pin, PORTS_PIN_MODE mode)
bool PLIB_USART_ExistsTransmitter(USART_MODULE_ID index)
void SYS_PORTS_InterruptEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_PIN_INTERRUPT_TYPE pinInterruptType)
TMR_PRESCALE DRV_TMR0_PrescalerGet(void)
DRV_TMR_CLIENT_STATUS DRV_TMR1_ClientStatus(void)
void PLIB_DMA_ChannelXStartAddressOffsetSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t address, DMA_ADDRESS_OFFSET_TYPE offset)
SYS_DMA_CHANNEL_CHAIN_PRIO
void * PLIB_USART_ReceiverAddressGet(USART_MODULE_ID index)
void SYS_PORTS_Toggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK toggleMask)
bool PLIB_DMA_ExistsSuspend(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelBits(DMA_MODULE_ID index)
void PLIB_SPI_BufferWrite16bit(SPI_MODULE_ID index, uint16_t data)
DRV_USART_TRANSFER_STATUS DRV_USART_TransferStatus(const DRV_HANDLE handle)
void SYS_PORTS_ChangeNotificationInIdleModeEnable(PORTS_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXCellProgressPointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_PORTS_ExistsPortsWrite(PORTS_MODULE_ID index)
bool PLIB_USART_TransmitterBufferIsFull(USART_MODULE_ID index)
bool PLIB_USART_ExistsReceiverAddress(USART_MODULE_ID index)
USART_OPERATION_MODE linesEnable
void DRV_USART_ByteErrorCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
uint32_t DRV_TMR3_CounterValueGet(void)
bool PLIB_DMA_LastBusAccessIsRead(DMA_MODULE_ID index)
bool PLIB_USART_BaudRateAutoDetectIsComplete(USART_MODULE_ID index)
void PLIB_USART_AddressSet(USART_MODULE_ID index, uint8_t address)
bool PLIB_PORTS_ExistsPinMode(PORTS_MODULE_ID index)
DMA_CHANNEL_TRANSFER_DIRECTION PLIB_DMA_ChannelXTransferDirectionGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
DRV_TMR_OPERATION_MODE DRV_TMR2_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void SYS_DEBUG_ErrorLevelSet(SYS_ERROR_LEVEL level)
void PLIB_DMA_ChannelXINTSourceEnable(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void DRV_TMR_Deinitialize(SYS_MODULE_OBJ object)
void PLIB_DMA_CRCBitOrderSelect(DMA_MODULE_ID index, DMA_CRC_BIT_ORDER bitOrder)
bool PLIB_DMA_ExistsChannelXINTSourceFlag(DMA_MODULE_ID index)
void SYS_PORTS_PinDirectionSelect(PORTS_MODULE_ID index, SYS_PORTS_PIN_DIRECTION pinDir, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
SPI_INPUT_SAMPLING_PHASE inputSamplePhase
bool PLIB_DMA_ExistsChannelXPatternLength(DMA_MODULE_ID index)
void SYS_DEBUG_Message(const char *message)
bool PLIB_USART_RunInOverflowIsEnabled(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticeEdgeControl(PORTS_MODULE_ID index)
void PLIB_DMA_CRCWriteByteOrderMaintain(DMA_MODULE_ID index)
DRV_SPI_BUFFER_EVENT_HANDLER operationStarting
uint32_t DRV_IC0_Capture32BitDataRead(void)
SYS_ERROR_LEVEL SYS_DEBUG_ErrorLevelGet(void)
void PLIB_DMA_ChannelXSourceSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t sourceSize)
SYS_MODULE_OBJ SYS_DMA_Initialize(const SYS_MODULE_INIT *const init)
static void qqqbitmapreset(qqnull_params)
void PLIB_USART_LineControlModeSelect(USART_MODULE_ID index, USART_LINECONTROL_MODE dataFlowConfig)
void SYS_PORTS_OpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_DMA_ChannelXDestinationSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t destinationSize)
static void DRV_TMR1_Close(void)
void DRV_USART_WriteByte(const DRV_HANDLE handle, const uint8_t byte)
static unsigned char qqqzzglobflag
void PLIB_PORTS_ChannelChangeNoticePullUpEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_USART_ExistsLineControlMode(USART_MODULE_ID index)
DRV_HANDLE DRV_USART0_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT ioIntent)
uint16_t PLIB_DMA_ChannelXPeripheralAddressGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_PinChangeNoticeEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_DMA_ChannelXSourceStartAddressSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint32_t sourceStartAddress)
void DRV_TMR1_PeriodValueSet(uint32_t value)
bool PLIB_PORTS_ExistsPinChangeNotice(PORTS_MODULE_ID index)
void DRV_SPI_Close(DRV_HANDLE handle)
bool PLIB_DMA_ExistsChannelXSourcePointer(DMA_MODULE_ID index)
SYS_MODULE_INIT moduleInit
static void qqbmsoutput(FILEPOINT char *s, unsigned int i)
void DRV_TMR1_StopInIdleEnable(void)
uint32_t DRV_TMR2_PeriodValueGet(void)
bool PLIB_DMA_CRCAppendModeIsEnabled(DMA_MODULE_ID index)
void PLIB_SPI_FramedCommunicationEnable(SPI_MODULE_ID index)
void PLIB_DMA_CRCAppendModeEnable(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsPinControl(SPI_MODULE_ID index)
SYS_MODULE_OBJ spiObjectIdx2
bool PLIB_PORTS_ExistsRemapInput(PORTS_MODULE_ID index)
SPI_AUDIO_TRANSMIT_MODE audioTransmitMode
void PLIB_DMA_ChannelXINTSourceDisable(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
bool PLIB_PORTS_ExistsAnPinsMode(PORTS_MODULE_ID index)
void DRV_USART_TasksTransmit(SYS_MODULE_OBJ object)
void PLIB_DMA_ChannelXStartIRQSet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRIGGER_SOURCE IRQnum)
void PLIB_SPI_AudioTransmitModeSelect(SPI_MODULE_ID index, SPI_AUDIO_TRANSMIT_MODE mode)
uintptr_t DRV_SPI_BUFFER_HANDLE
uint32_t DRV_TMR_AlarmPeriodGet(DRV_HANDLE handle)
bool PLIB_DMA_ExistsChannelXAbortIRQ(DMA_MODULE_ID index)
void PLIB_SPI_FrameSyncPulsePolaritySelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_POLARITY polarity)
bool DRV_TMR_Start(DRV_HANDLE handle)
bool PLIB_DMA_ExistsChannelXINTSource(DMA_MODULE_ID index)
bool PLIB_USART_ExistsRunInOverflow(USART_MODULE_ID index)
static int adc_63zqqzqz(qqnull_params)
void DRV_TMR3_CounterClear(void)
uint32_t DRV_TMR_AlarmHasElapsed(DRV_HANDLE handle)
void PLIB_SPI_FrameSyncPulseWidthSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_WIDTH width)
bool PLIB_DMA_ExistsChannelXSourceSize(DMA_MODULE_ID index)
DRV_HANDLE DRV_USART_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT ioIntent)
SYS_MODULE_OBJ drvUSBObject
void SYS_DMA_TasksErrorISR(SYS_MODULE_OBJ object, DMA_CHANNEL activeChannel)
void APP_Initialize(void)
SPI_AUDIO_PROTOCOL audioProtocolMode
void PLIB_PORTS_CnPinsPullUpDisable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
static void DRV_TMR3_DeInitialize(void)
void SYS_DMA_ChannelTransferSet(SYS_DMA_CHANNEL_HANDLE handle, const void *srcAddr, size_t srcSize, const void *destAddr, size_t destSize, size_t cellSize)
DRV_SPI_CLOCK_MODE clockMode
bool PLIB_PORTS_ChangeNoticePerPortHasOccurred(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_SPI_BufferWrite32bit(SPI_MODULE_ID index, uint32_t data)
bool PLIB_PORTS_ExistsChangeNoticePullDownPerPort(PORTS_MODULE_ID index)
void SYS_PORTS_PinSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_USART_BaudRateHighSet(USART_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
static DRV_TMR_OPERATION_MODE DRV_TMR3_OperationModeGet(void)
void SYS_PORTS_ChangeNotificationGlobalDisable(PORTS_MODULE_ID index)
bool PLIB_DMA_ChannelXINTSourceFlagGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
bool PLIB_USART_ExistsBRGClockSourceSelect(USART_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR0_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void DRV_TMR2_CounterClear(void)
static void qqoutput(FILEPOINT char *s, int i)
bool PLIB_SPI_ExistsFramedCommunication(SPI_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePullUpPerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool DRV_USART_TransmitBufferIsFull(const DRV_HANDLE handle)
bool PLIB_DMA_ChannelXBusyIsBusy(DMA_MODULE_ID index, DMA_CHANNEL channel)
SYS_MODULE_OBJ DRV_USART0_Initialize(void)
void PLIB_PORTS_RemapOutput(PORTS_MODULE_ID index, PORTS_REMAP_OUTPUT_FUNCTION outputFunction, PORTS_REMAP_OUTPUT_PIN remapOutputPin)
static int adc_63zqzqzq(int qqqi)
uint32_t DRV_TMR_CounterValueGet(DRV_HANDLE handle)
uintptr_t SYS_DMA_CHANNEL_HANDLE
void PLIB_DMA_ChannelXBusyInActiveSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsOperationMode(USART_MODULE_ID index)
void SYS_DMA_ChannelCRCSet(SYS_DMA_CHANNEL_HANDLE handle, SYS_DMA_CHANNEL_OPERATION_MODE_CRC crc)
void DRV_USART_BufferAddRead(const DRV_HANDLE handle, DRV_USART_BUFFER_HANDLE *const bufferHandle, void *buffer, const size_t size)
void PLIB_DMA_ChannelXPatternIgnoreByteEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_USART_Transmitter9BitsSend(USART_MODULE_ID index, int8_t data, bool Bit9th)
void DRV_SPI_Tasks(SYS_MODULE_OBJ object)
void PLIB_DMA_CRCChannelSelect(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint16_t PLIB_DMA_ChannelXCellSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void SYS_PORTS_Clear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK clearMask)
void SYS_DMA_ChannelEnable(SYS_DMA_CHANNEL_HANDLE handle)
size_t DRV_USART_Write(const DRV_HANDLE handle, void *buffer, const size_t numbytes)
uint16_t DRV_IC0_Capture16BitDataRead(void)
static void qqqupload(qqnull_params)
SYS_STATUS DRV_USART0_Status(void)
void PLIB_DMA_ChannelXDestinationAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_DESTINATION_ADDRESSING_MODE destinationAddressMode)
void SYS_PORTS_DirectionSelect(PORTS_MODULE_ID index, SYS_PORTS_PIN_DIRECTION pinDir, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_SPI_TransmitUnderRunStatusGet(SPI_MODULE_ID index)
void PLIB_PORTS_CnPinsEnable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
void DRV_USART_AddressedBufferAddWrite(const DRV_HANDLE hClient, DRV_USART_BUFFER_HANDLE *bufferHandle, uint8_t address, void *source, size_t nWords)
void PLIB_PORTS_ChangeNoticePullDownPerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool DRV_TMR2_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
bool PLIB_DMA_ChannelXChainIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_SPI_AudioErrorDisable(SPI_MODULE_ID index, SPI_AUDIO_ERROR error)
uint32_t DRV_TMR0_PeriodValueGet(void)
bool PLIB_PORTS_ExistsChangeNoticePullUpPerPort(PORTS_MODULE_ID index)
uint32_t DRV_ADC_SamplesRead(uint8_t bufIndex)
bool DRV_TMR3_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
ldra_void_function qqqaccumupload[QQQnumfil]
uint32_t PLIB_DMA_ChannelXSourceStartAddressGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void SYS_DEBUG_Print(const char *format,...)
INT_SOURCE rxInterruptSource
bool SYS_PORTS_PinLatchedGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
SYS_MODULE_OBJ DRV_IC_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
PORTS_DATA_TYPE PLIB_PORTS_ReadLatched(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void SYS_PORTS_PinWrite(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, bool value)
void DRV_USART0_TasksTransmit(void)
uint32_t DRV_TMR0_CounterFrequencyGet(void)
void PLIB_SPI_StopInIdleEnable(SPI_MODULE_ID index)
bool PLIB_USART_ExistsTransmitterInterruptMode(USART_MODULE_ID index)
void PLIB_SPI_BaudRateClockSelect(SPI_MODULE_ID index, SPI_BAUD_RATE_CLOCK type)
bool PLIB_SPI_ExistsOutputDataPhase(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsEnableControl(DMA_MODULE_ID index)
DMA_CHANNEL_PRIORITY PLIB_DMA_ChannelPriorityGet(DMA_MODULE_ID index)
bool PLIB_USART_ExistsModuleBusyStatus(USART_MODULE_ID index)
void PLIB_DMA_ChannelXBusyActiveSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_Write(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value)
bool PLIB_DMA_ExistsChannelXBusy(DMA_MODULE_ID index)
void PLIB_USART_TransmitterInterruptModeSelect(USART_MODULE_ID index, USART_TRANSMIT_INTR_MODE fifolevel)
DRV_TMR_OPERATION_MODE DRV_TMR3_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
bool PLIB_USART_ReceiverIsIdle(USART_MODULE_ID index)
void PLIB_PORTS_PinChangeNoticePerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uint32_t DRV_IC_Capture32BitDataRead(DRV_HANDLE handle)
void PLIB_DMA_BusyActiveReset(DMA_MODULE_ID index)
INT_SOURCE errInterruptSource
void DRV_USART_BufferAddWrite(const DRV_HANDLE handle, DRV_USART_BUFFER_HANDLE *bufferHandle, void *buffer, const size_t size)
void PLIB_SPI_SlaveSelectEnable(SPI_MODULE_ID index)
SYS_MODULE_OBJ SYS_DEBUG_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
ldra_void_function qqqaccumreset[QQQnumfil]
SYS_MODULE_INIT moduleInit
void SYS_DMA_ChannelSetup(SYS_DMA_CHANNEL_HANDLE handle, SYS_DMA_CHANNEL_OP_MODE modeEnable, DMA_TRIGGER_SOURCE eventSrc)
PORTS_DATA_TYPE PLIB_PORTS_Read(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
SYS_MODULE_INDEX consoleIndex
void PLIB_USART_Enable(USART_MODULE_ID index)
static void DRV_TMR4_Tasks(void)
DRV_USART_OPERATION_MODE mode
bool PLIB_DMA_ChannelXINTSourceIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
SYS_STATUS DRV_SPI_Status(SYS_MODULE_OBJ object)
void PLIB_DMA_ChannelXTransferCountSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t transferCount)
void PLIB_DMA_ChannelXAutoDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ReceiverDataIsAvailable(USART_MODULE_ID index)
DMA_CHANNEL dmaChannelTransmit
DRV_USART_BAUD_SET_RESULT DRV_USART_BaudSet(const DRV_HANDLE client, uint32_t baud)
void SYS_PORTS_ChangeNotificationPullUpEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
DMA_CRC_BYTE_ORDER byteOrder
SYS_MODULE_OBJ usbDevObject0
void DRV_TMR0_Initialize(void)
bool PLIB_USART_ExistsTransmitterEnable(USART_MODULE_ID index)
bool PLIB_SPI_ExistsBaudRateClock(SPI_MODULE_ID index)
static int qqqqbmselwidth
void PLIB_SPI_Enable(SPI_MODULE_ID index)
SYS_MODULE_OBJ DRV_SPI_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
uint16_t PLIB_DMA_ChannelXSourceSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
INT_SOURCE interruptError
uint16_t PLIB_DMA_ChannelXTransferCountGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ExistsChannelXStartIRQ(DMA_MODULE_ID index)
void DRV_TMR1_Initialize(void)
DRV_TMR_OPERATION_MODE DRV_TMR_OperationModeGet(DRV_HANDLE handle)
uint32_t DRV_TMR0_CounterValueGet(void)
void PLIB_DMA_ChannelXPatternIgnoreByteDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_TMR3_CounterValueSet(uint32_t value)
DRV_USART_LINE_CONTROL_SET_RESULT DRV_USART_LineControlSet(const DRV_HANDLE client, const DRV_USART_LINE_CONTROL lineControl)
bool PLIB_DMA_ExistsChannelXAuto(DMA_MODULE_ID index)
void SYS_PORTS_PinOpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool DRV_TMR1_Start(void)
void PLIB_SPI_AudioProtocolEnable(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXPatternLengthSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_PATTERN_LENGTH patternLen)
bool DRV_SPIn_TransmitterBufferIsFull(void)
void SYS_DMA_TasksError(SYS_MODULE_OBJ object)
void PLIB_USART_ReceiverDisable(USART_MODULE_ID index)
DRV_SPI_TASK_MODE taskMode
bool PLIB_USART_ExistsRunInSleepMode(USART_MODULE_ID index)
void qqpopulate_array_fcn_ptrQQ(int x, ldra_void_function y, ldra_void_function z)
bool PLIB_PORTS_ExistsPortsRead(PORTS_MODULE_ID index)
DMA_CHANNEL PLIB_DMA_CRCChannelGet(DMA_MODULE_ID index)
DRV_HANDLE DRV_TMR_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT intent)
void PLIB_DMA_ChannelXNullWriteModeDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_TransmitterBreakSendIsComplete(USART_MODULE_ID index)
bool PLIB_SPI_ExistsFrameSyncPulseCounter(SPI_MODULE_ID index)
bool PLIB_USART_ReceiverOverrunHasOccurred(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsPinChangeNoticePerPort(PORTS_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXPatternIgnoreByte(DMA_MODULE_ID index)
void SYS_PORTS_PinToggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_SPI_ExistsReceiveFIFOStatus(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXPriority(DMA_MODULE_ID index)
void DRV_USART_ByteTransmitCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
void DRV_TMR0_StopInIdleDisable(void)
void PLIB_USART_ReceiverIdleStateLowEnable(USART_MODULE_ID index)
static void DRV_TMR4_Open(void)
bool PLIB_DMA_ChannelXIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_USART_InitializeModeGeneral(USART_MODULE_ID index, bool autobaud, bool loopBackMode, bool wakeFromSleep, bool irdaMode, bool stopInIdle)
void PLIB_DMA_ChannelXDestinationStartAddressSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint32_t destinationStartAddress)
DMA_CHANNEL_INT_SOURCE PLIB_DMA_ChannelXTriggerSourceNumberGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ExistsChannelXChain(DMA_MODULE_ID index)
void PLIB_SPI_OutputDataPhaseSelect(SPI_MODULE_ID index, SPI_OUTPUT_DATA_PHASE phase)
#define DRV_IC_Close(handle)
unsigned int DRV_USART0_ReceiverBufferSizeGet(void)
static DRV_TMR_OPERATION_MODE DRV_TMR1_OperationModeGet(void)
void SYS_PORTS_ChangeNotificationDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void DRV_TMR4_CounterValueSet(uint32_t value)
void SYS_DMA_ChannelResume(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_DMA_ChannelXTransferDirectionSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRANSFER_DIRECTION chTransferDirection)
bool PLIB_USART_ExistsHandshakeMode(USART_MODULE_ID index)
void SYS_PORTS_PinPullDownDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddRead2(DRV_HANDLE handle, void *rxBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
SPI_FRAME_SYNC_PULSE frameSyncPulse
bool PLIB_PORTS_PinChangeNoticeEdgeIsEnabled(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_CHANGE_NOTICE_EDGE cnEdgeType)
void PLIB_USART_TransmitterIdleIsLowEnable(USART_MODULE_ID index)
bool PLIB_DMA_ExistsCRCChannel(DMA_MODULE_ID index)
uint8_t DRV_PMP0_Read(void)
void PLIB_DMA_ChannelXOperatingTransferModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRANSFER_MODE channeltransferMode)
bool PLIB_USART_ExistsReceiverAddressMask(USART_MODULE_ID index)
uint32_t PLIB_USART_BaudRateGet(USART_MODULE_ID index, int32_t clockFrequency)
bool PLIB_DMA_ExistsChannelXSourceStartAddress(DMA_MODULE_ID index)
static void DRV_TMR2_Open(void)
uint32_t DRV_TMR1_CounterFrequencyGet(void)
TMR_PRESCALE DRV_TMR1_PrescalerGet(void)
void PLIB_DMA_ChannelXChainToLower(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ExistsChannelXDestinationStartAddress(DMA_MODULE_ID index)
static void DRV_TMR4_DeInitialize(void)
void PLIB_USART_InitializeOperation(USART_MODULE_ID index, USART_RECEIVE_INTR_MODE receiveInterruptMode, USART_TRANSMIT_INTR_MODE transmitInterruptMode, USART_OPERATION_MODE operationMode)
void * PLIB_SPI_BufferAddressGet(SPI_MODULE_ID index)
void SYS_PORTS_PinClear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool SYS_DMA_IsBusy(void)
bool PLIB_SPI_ExistsFrameSyncPulseEdge(SPI_MODULE_ID index)
bool DRV_TMR4_Start(void)
void SYS_DMA_ChannelRelease(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_USART_ReceiverOverrunErrorClear(USART_MODULE_ID index)
void PLIB_DMA_ChannelXReloadDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_DEBUG_Reinitialize(SYS_MODULE_OBJ object, const SYS_MODULE_INIT *const init)
bool PLIB_USART_ExistsReceiverAddressAutoDetect(USART_MODULE_ID index)
void SYS_PORTS_RemapOutput(PORTS_MODULE_ID index, PORTS_REMAP_OUTPUT_FUNCTION function, PORTS_REMAP_OUTPUT_PIN remapPin)
bool PLIB_SPI_FIFOShiftRegisterIsEmpty(SPI_MODULE_ID index)